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NEWBIE ASKING FOR HELP! can anybody take a look at my Synopsys DC report?

 
 
walala
Guest
Posts: n/a
 
      09-13-2003
Dear all,

I am really a newbie in learning this IC design kind of stuff... After my
synthesis run for one day, I got the following resource REPORT FILE. I want
to count the number of my multipliers in this circuit... I counted the
number of multipliers is 8, am I right?

But when I looked at the synopsys LOG FILE, I again counted the number of
multipliers, it came out to be 64... which one is correct? Can anybody tell
me?


RESOURCE REPORT FILE:
----------------------------------------------------------------------------
--------------------
Information: Updating design information... (UID-85)
Warning: Design 'myidct' contains 1 high-fanout nets. A fanout number of
1000 will be used for delay calculations involving these nets. (TIM-134)

****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : myidct
Version: 2001.08-SP2
Date : Sat Sep 13 03:59:40 2003
****************************************

# A fanout number of 1000 was used for high fanout net computations.

Operating Conditions:
Wire Load Model Mode: top

Startpoint: count_reg[5]
(rising edge-triggered flip-flop)
Endpoint: count[5] (output port)
Path Group: (none)
Path Type: max

Point Incr Path
-----------------------------------------------------------
count_reg[5]/CLK (dffacs2) 0.00 # 0.00 r
count_reg[5]/Q (dffacs2) 0.25 0.25 f
count[5] (out) 0.00 0.25 f
data arrival time 0.25
-----------------------------------------------------------
(Path is unconstrained)


1

****************************************
Report : area
Design : myidct
Version: 2001.08-SP2
Date : Sat Sep 13 03:59:40 2003
****************************************

Library(s) Used:

lec25dscc25_TT (File:
/package/cae/cadence/cells/lec25sc25.rev6355/lec25dscc25/synopsys/lec25dscc2
5_TT.db)

Number of ports: 90
Number of nets: 12043
Number of cells: 9826
Number of references: 61

Combinational area: 827714.750000
Noncombinational area: 383217.875000
Net Interconnect area: undefined (No wire load specified)

Total cell area: 1210932.625000
Total area: undefined
1

****************************************
Report : resources
Design : myidct
Version: 2001.08-SP2
Date : Sat Sep 13 03:59:41 2003
****************************************

Resource Sharing Report for design myidct in file
/home/min/a/xding/EE495d/Lab4/source/myidct.vhd

================================================== ==========================
===
| | | | Contained |
|
| Resource | Module | Parameters | Resources | Contained
Operations |
================================================== ==========================
===
| r193 | DW01_addsub | width=25 | | add_128
|
| | | | | add_152/plus/plus
|
| | | | | add_160
|
| | | | | add_179/plus/plus
|
| | | | | add_200/plus/plus
|
| | | | | sub_111 sub_117
|
| | | | | sub_123
|
| r194 | DW01_addsub | width=24 | | add_108 add_114
|
| | | | | add_142_853 add_191
|
| | | | | sub_120 sub_126
|
| | | | | sub_159_804
|
| | | | | sub_174_660
|
| r202 | DW01_inc | width=6 | | add_214/plus/plus
|
| r206 | DW02_mult | B_width=24 | |
mul_108/$vhdl_mult_const_1129_1378 |
| | | |
| | | A_width=8 | |
mul_114/$vhdl_mult_const_1129_1238 |
| | | |
| | | | |
mul_120/$vhdl_mult_const_1129_1101 |
| | | |
| | | | |
mul_126/$vhdl_mult_const_1129_962 |
| | | |
| | | | |
mul_142/$vhdl_mult_const_1129_865 |
| | | |
| | | | |
mul_159/$vhdl_mult_const_1129_816 |
| | | |
| | | | |
mul_174/$vhdl_mult_const_1129_672 |
| | | |
| | | | |
mul_191/$vhdl_mult_const_1129_623 |
| r579 | DW01_addsub | width=25 | | add_110 add_116
|
| | | | | add_122
|
| | | | | add_147/plus/plus
|
| | | | | add_163/plus/plus
|
| | | | | add_184/plus/plus
|
| | | | | add_195/plus/plus
|
| | | | | sub_129
|
| r580 | DW02_mult | B_width=24 | |
mul_109/$vhdl_mult_const_1129_1427 |
| | | |
| | | A_width=8 | |
mul_115/$vhdl_mult_const_1129_1287 |
| | | |
| | | | |
mul_121/$vhdl_mult_const_1129_1148 |
| | | |
| | | | |
mul_127/$vhdl_mult_const_1129_1010 |
| | | |
| | | | |
mul_143/$vhdl_mult_const_1129_901 |
| | | |
| | | | |
mul_158/$vhdl_mult_const_1129_755 |
| | | |
| | | | |
mul_174/$vhdl_mult_const_1129_659 |
| | | |
| | | | |
mul_191/$vhdl_mult_const_1129_611 |
| r581 | DW02_mult | B_width=24 | |
mul_109/$vhdl_mult_const_1129_1414 |
| | | |
| | | A_width=8 | |
mul_115/$vhdl_mult_const_1129_1274 |
| | | |
| | | | |
mul_121/$vhdl_mult_const_1129_1136 |
| | | |
| | | | |
mul_126/$vhdl_mult_const_1129_950 |
| | | |
| | | | |
mul_143/$vhdl_mult_const_1129_914 |
| | | |
| | | | |
mul_158/$vhdl_mult_const_1129_767 |
| | | |
| | | | |
mul_175/$vhdl_mult_const_1129_719 |
| | | |
| | | | |
mul_190/$vhdl_mult_const_1129_575 |
| r582 | DW02_mult | B_width=24 | |
mul_108/$vhdl_mult_const_1129_1365 |
| | | |
| | | A_width=8 | |
mul_114/$vhdl_mult_const_1129_1226 |
| | | |
| | | | |
mul_120/$vhdl_mult_const_1129_1088 |
| | | |
| | | | |
mul_127/$vhdl_mult_const_1129_998 |
| | | |
| | | | |
mul_143/$vhdl_mult_const_1129_889 |
| | | |
| | | | |
mul_159/$vhdl_mult_const_1129_791 |
| | | |
| | | | |
mul_174/$vhdl_mult_const_1129 |
| | | |
mul_191/$vhdl_mult_const_1129_599 |
| r583 | DW02_mult | B_width=24 | |
mul_108/$vhdl_mult_const_1129 |
| | A_width=8 | |
mul_115/$vhdl_mult_const_1129 |
| | | |
mul_121/$vhdl_mult_const_1129_1124 |
| | | |
| | | | |
mul_127/$vhdl_mult_const_1129_986 |
| | | |
| | | | |
mul_142/$vhdl_mult_const_1129_852 |
| | | |
| | | | |
mul_159/$vhdl_mult_const_1129_803 |
| | | |
| | | | |
mul_175/$vhdl_mult_const_1129_707 |
| | | |
| | | | |
mul_190/$vhdl_mult_const_1129_563 |
| r584 | DW02_mult | B_width=24 | |
mul_109/$vhdl_mult_const_1129_1402 |
| | | |
| | | A_width=8 | |
mul_114/$vhdl_mult_const_1129_1214 |
| | | |
| | | | |
mul_120/$vhdl_mult_const_1129 |
| | | |
mul_126/$vhdl_mult_const_1129 |
| | | |
mul_142/$vhdl_mult_const_1129 |
| | | |
mul_159/$vhdl_mult_const_1129 |
| | | |
mul_174/$vhdl_mult_const_1129_647 |
| | | |
| | | | |
mul_190/$vhdl_mult_const_1129 |
| r585 | DW02_mult | B_width=24 | |
mul_108/$vhdl_mult_const_1129_1353 |
| | | |
| | | A_width=8 | |
mul_114/$vhdl_mult_const_1129 |
| | | |
mul_120/$vhdl_mult_const_1129_1076 |
| | | |
| | | | |
mul_126/$vhdl_mult_const_1129_938 |
| | | |
| | | | |
mul_143/$vhdl_mult_const_1129 |
| | | |
mul_158/$vhdl_mult_const_1129 |
| | | |
mul_175/$vhdl_mult_const_1129_695 |
| | | |
| | | | |
mul_190/$vhdl_mult_const_1129_551 |
| r586 | DW02_mult | B_width=24 | |
mul_109/$vhdl_mult_const_1129 |
| | A_width=8 | |
mul_115/$vhdl_mult_const_1129_1262 |
| | | |
| | | | |
mul_121/$vhdl_mult_const_1129 |
| | | |
mul_127/$vhdl_mult_const_1129 |
| | | |
mul_142/$vhdl_mult_const_1129_840 |
| | | |
| | | | |
mul_158/$vhdl_mult_const_1129_743 |
| | | |
| | | | |
mul_175/$vhdl_mult_const_1129 |
| | | |
mul_191/$vhdl_mult_const_1129 |
| r588 | DW01_addsub | width=24 | | add_108_1379
|
| | | | | add_121_1149
add_144 |
| | | | | add_168/plus/plus
|
| | | | | sub_114_1239
|
| | | | | sub_127_1011
sub_177 |
| | | | | sub_193
|
| r589 | DW01_addsub | width=24 | | add_109_1428
add_120 |
| | | | | add_176 add_192
|
| | | | | sub_115_1288
|
| | | | | sub_126_963 sub_145
|
| | | | | sub_161
|
| r591 | DW01_addsub | width=24 | | add_109_1415
add_127 |
| | | | | add_143_915
|
| | | | | add_175_720
|
| | | | | sub_115_1275
|
| | | | | sub_120_1089
|
| | | | | sub_158_768
|
| | | | | sub_191_624
|
| r592 | DW01_addsub | width=24 | | add_108_1366
add_121 |
| | | | | add_126 add_142_866
|
| | | | | add_174 sub_114
|
| | | | | sub_159_817
|
| | | | | sub_190_576
|
| r593 | DW01_addsub | width=24 | | add_109 add_143_902
|
| | | | | add_175 add_190
|
| | | | | sub_115 sub_121
|
| | | | | sub_127 sub_158
|
| r594 | DW01_addsub | width=24 | | add_143 add_158
|
| | | | | sub_175 sub_190
|
| r595 | DW01_addsub | width=24 | | add_142 sub_159
|
| | | | | sub_174 sub_191
|
================================================== ==========================
===


Implementation Report

================================================== ==========================
=
| | | Current | Set
|
| Cell | Module | Implementation | Implementation
|
================================================== ==========================
=
| add_214/plus/plus | DW01_inc | rpl |
|
| r193 | DW01_addsub | rpl |
|
| r194 | DW01_addsub | rpl |
|
| r206 | DW02_mult | csa |
|
| r579 | DW01_addsub | rpl |
|
| r580 | DW02_mult | csa |
|
| r581 | DW02_mult | csa |
|
| r582 | DW02_mult | csa |
|
| r583 | DW02_mult | csa |
|
| r584 | DW02_mult | csa |
|
| r585 | DW02_mult | csa |
|
| r586 | DW02_mult | csa |
|
| r588 | DW01_addsub | rpl |
|
| r589 | DW01_addsub | rpl |
|
| r591 | DW01_addsub | rpl |
|
| r592 | DW01_addsub | rpl |
|
| r593 | DW01_addsub | rpl |
|
| r594 | DW01_addsub | rpl |
|
| r595 | DW01_addsub | rpl |
|
================================================== ==========================
=

No multiplexors to report


***************************************
Design : myidct_DW01_inc_6_0
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW02_mult_8_24_7
***************************************


Resource Sharing Report for design DW02_mult_8_24

================================================== ==========================
===
| | | | Contained |
|
| Resource | Module | Parameters | Resources | Contained
Operations |
================================================== ==========================
===
| r46 | DW01_add | width=30 | | FS
|
================================================== ==========================
===


Implementation Report

================================================== ==========================
=
| | | Current | Set
|
| Cell | Module | Implementation | Implementation
|
================================================== ==========================
=
| FS | DW01_add | cla | cla
|
================================================== ==========================
=

No multiplexors to report


***************************************
Design : myidct_DW01_add_30_7
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW02_mult_8_24_6
***************************************


Resource Sharing Report for design DW02_mult_8_24

================================================== ==========================
===
| | | | Contained |
|
| Resource | Module | Parameters | Resources | Contained
Operations |
================================================== ==========================
===
| r46 | DW01_add | width=30 | | FS
|
================================================== ==========================
===


Implementation Report

================================================== ==========================
=
| | | Current | Set
|
| Cell | Module | Implementation | Implementation
|
================================================== ==========================
=
| FS | DW01_add | cla | cla
|
================================================== ==========================
=

No multiplexors to report


***************************************
Design : myidct_DW01_add_30_6
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW02_mult_8_24_5
***************************************


Resource Sharing Report for design DW02_mult_8_24

================================================== ==========================
===
| | | | Contained |
|
| Resource | Module | Parameters | Resources | Contained
Operations |
================================================== ==========================
===
| r46 | DW01_add | width=30 | | FS
|
================================================== ==========================
===


Implementation Report

================================================== ==========================
=
| | | Current | Set
|
| Cell | Module | Implementation | Implementation
|
================================================== ==========================
=
| FS | DW01_add | cla | cla
|
================================================== ==========================
=

No multiplexors to report


***************************************
Design : myidct_DW01_add_30_5
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW02_mult_8_24_4
***************************************


Resource Sharing Report for design DW02_mult_8_24

================================================== ==========================
===
| | | | Contained |
|
| Resource | Module | Parameters | Resources | Contained
Operations |
================================================== ==========================
===
| r46 | DW01_add | width=30 | | FS
|
================================================== ==========================
===


Implementation Report

================================================== ==========================
=
| | | Current | Set
|
| Cell | Module | Implementation | Implementation
|
================================================== ==========================
=
| FS | DW01_add | cla | cla
|
================================================== ==========================
=

No multiplexors to report


***************************************
Design : myidct_DW01_add_30_4
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW02_mult_8_24_3
***************************************


Resource Sharing Report for design DW02_mult_8_24

================================================== ==========================
===
| | | | Contained |
|
| Resource | Module | Parameters | Resources | Contained
Operations |
================================================== ==========================
===
| r46 | DW01_add | width=30 | | FS
|
================================================== ==========================
===


Implementation Report

================================================== ==========================
=
| | | Current | Set
|
| Cell | Module | Implementation | Implementation
|
================================================== ==========================
=
| FS | DW01_add | cla | cla
|
================================================== ==========================
=

No multiplexors to report


***************************************
Design : myidct_DW01_add_30_3
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW02_mult_8_24_2
***************************************


Resource Sharing Report for design DW02_mult_8_24

================================================== ==========================
===
| | | | Contained |
|
| Resource | Module | Parameters | Resources | Contained
Operations |
================================================== ==========================
===
| r46 | DW01_add | width=30 | | FS
|
================================================== ==========================
===


Implementation Report

================================================== ==========================
=
| | | Current | Set
|
| Cell | Module | Implementation | Implementation
|
================================================== ==========================
=
| FS | DW01_add | cla | cla
|
================================================== ==========================
=

No multiplexors to report


***************************************
Design : myidct_DW01_add_30_2
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW02_mult_8_24_1
***************************************


Resource Sharing Report for design DW02_mult_8_24

================================================== ==========================
===
| | | | Contained |
|
| Resource | Module | Parameters | Resources | Contained
Operations |
================================================== ==========================
===
| r46 | DW01_add | width=30 | | FS
|
================================================== ==========================
===


Implementation Report

================================================== ==========================
=
| | | Current | Set
|
| Cell | Module | Implementation | Implementation
|
================================================== ==========================
=
| FS | DW01_add | cla | cla
|
================================================== ==========================
=

No multiplexors to report


***************************************
Design : myidct_DW01_add_30_1
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW02_mult_8_24_0
***************************************


Resource Sharing Report for design DW02_mult_8_24

================================================== ==========================
===
| | | | Contained |
|
| Resource | Module | Parameters | Resources | Contained
Operations |
================================================== ==========================
===
| r46 | DW01_add | width=30 | | FS
|
================================================== ==========================
===


Implementation Report

================================================== ==========================
=
| | | Current | Set
|
| Cell | Module | Implementation | Implementation
|
================================================== ==========================
=
| FS | DW01_add | cla | cla
|
================================================== ==========================
=

No multiplexors to report


***************************************
Design : myidct_DW01_add_30_0
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW01_addsub_25_1
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW01_addsub_25_0
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW01_addsub_24_7
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW01_addsub_24_6
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW01_addsub_24_5
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW01_addsub_24_4
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW01_addsub_24_3
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW01_addsub_24_2
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW01_addsub_24_1
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report


***************************************
Design : myidct_DW01_addsub_24_0
***************************************


No resource sharing information to report.

No implementations to report

No multiplexors to report
1
 
Reply With Quote
 
 
 
 
walala
Guest
Posts: n/a
 
      09-13-2003
From the naming pattern of the "mul_8_24_x", it is easily seen that it has
64 multipliers...

---------------------------------------------------------------------------

Warning: In design 'myidct_DW02_mult_8_24_7', port 'A[7]' is not connected
to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_7', port 'TC' is not connected to
any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[31]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[30]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[29]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[28]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[27]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[26]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[25]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[24]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_7', a pin on submodule 'FS' is
connected to logic 1 or logic 0. (LINT-32)
Pin 'B[6]' is connected to logic 0.
Pin 'B[5]' is connected to logic 0.
Pin 'B[4]' is connected to logic 0.
Pin 'B[3]' is connected to logic 0.
Pin 'B[2]' is connected to logic 0.
Pin 'B[1]' is connected to logic 0.
Pin 'B[0]' is connected to logic 0.
Pin 'CI' is connected to logic 0.
Warning: In design 'myidct_DW02_mult_8_24_7', the same net is connected to
more than one pin on submodule 'FS'. (LINT-33)
Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
Warning: In design 'myidct_DW02_mult_8_24_6', port 'A[7]' is not connected
to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_6', port 'TC' is not connected to
any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[31]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[30]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[29]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[28]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[27]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[26]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[25]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[24]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_6', a pin on submodule 'FS' is
connected to logic 1 or logic 0. (LINT-32)
Pin 'B[6]' is connected to logic 0.
Pin 'B[5]' is connected to logic 0.
Pin 'B[4]' is connected to logic 0.
Pin 'B[3]' is connected to logic 0.
Pin 'B[2]' is connected to logic 0.
Pin 'B[1]' is connected to logic 0.
Pin 'B[0]' is connected to logic 0.
Pin 'CI' is connected to logic 0.
Warning: In design 'myidct_DW02_mult_8_24_6', the same net is connected to
more than one pin on submodule 'FS'. (LINT-33)
Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
Warning: In design 'myidct_DW02_mult_8_24_5', port 'A[7]' is not connected
to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_5', port 'TC' is not connected to
any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[31]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[30]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[29]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[28]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[27]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[26]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[25]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[24]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_5', a pin on submodule 'FS' is
connected to logic 1 or logic 0. (LINT-32)
Pin 'B[6]' is connected to logic 0.
Pin 'B[5]' is connected to logic 0.
Pin 'B[4]' is connected to logic 0.
Pin 'B[3]' is connected to logic 0.
Pin 'B[2]' is connected to logic 0.
Pin 'B[1]' is connected to logic 0.
Pin 'B[0]' is connected to logic 0.
Pin 'CI' is connected to logic 0.
Warning: In design 'myidct_DW02_mult_8_24_5', the same net is connected to
more than one pin on submodule 'FS'. (LINT-33)
Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
Warning: In design 'myidct_DW02_mult_8_24_4', port 'A[7]' is not connected
to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_4', port 'TC' is not connected to
any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[31]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[30]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[29]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[28]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[27]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[26]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[25]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[24]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_4', a pin on submodule 'FS' is
connected to logic 1 or logic 0. (LINT-32)
Pin 'B[6]' is connected to logic 0.
Pin 'B[5]' is connected to logic 0.
Pin 'B[4]' is connected to logic 0.
Pin 'B[3]' is connected to logic 0.
Pin 'B[2]' is connected to logic 0.
Pin 'B[1]' is connected to logic 0.
Pin 'B[0]' is connected to logic 0.
Pin 'CI' is connected to logic 0.
Warning: In design 'myidct_DW02_mult_8_24_4', the same net is connected to
more than one pin on submodule 'FS'. (LINT-33)
Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
Warning: In design 'myidct_DW02_mult_8_24_3', port 'A[7]' is not connected
to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_3', port 'TC' is not connected to
any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[31]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[30]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[29]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[28]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[27]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[26]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[25]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[24]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_3', a pin on submodule 'FS' is
connected to logic 1 or logic 0. (LINT-32)
Pin 'B[6]' is connected to logic 0.
Pin 'B[5]' is connected to logic 0.
Pin 'B[4]' is connected to logic 0.
Pin 'B[3]' is connected to logic 0.
Pin 'B[2]' is connected to logic 0.
Pin 'B[1]' is connected to logic 0.
Pin 'B[0]' is connected to logic 0.
Pin 'CI' is connected to logic 0.
Warning: In design 'myidct_DW02_mult_8_24_3', the same net is connected to
more than one pin on submodule 'FS'. (LINT-33)
Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
Warning: In design 'myidct_DW02_mult_8_24_2', port 'A[7]' is not connected
to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_2', port 'A[2]' is not connected
to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_2', port 'TC' is not connected to
any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[31]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[30]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[29]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[28]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[27]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[26]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[25]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[24]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_2', a pin on submodule 'FS' is
connected to logic 1 or logic 0. (LINT-32)
Pin 'B[6]' is connected to logic 0.
Pin 'B[5]' is connected to logic 0.
Pin 'B[4]' is connected to logic 0.
Pin 'B[3]' is connected to logic 0.
Pin 'B[2]' is connected to logic 0.
Pin 'B[1]' is connected to logic 0.
Pin 'B[0]' is connected to logic 0.
Pin 'CI' is connected to logic 0.
Warning: In design 'myidct_DW02_mult_8_24_2', the same net is connected to
more than one pin on submodule 'FS'. (LINT-33)
Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
Warning: In design 'myidct_DW02_mult_8_24_1', port 'A[7]' is not connected
to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_1', port 'A[4]' is not connected
to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_1', port 'TC' is not connected to
any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[31]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[30]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[29]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[28]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[27]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[26]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[25]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[24]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_1', a pin on submodule 'FS' is
connected to logic 1 or logic 0. (LINT-32)
Pin 'B[6]' is connected to logic 0.
Pin 'B[5]' is connected to logic 0.
Pin 'B[4]' is connected to logic 0.
Pin 'B[3]' is connected to logic 0.
Pin 'B[2]' is connected to logic 0.
Pin 'B[1]' is connected to logic 0.
Pin 'B[0]' is connected to logic 0.
Pin 'CI' is connected to logic 0.
Warning: In design 'myidct_DW02_mult_8_24_1', the same net is connected to
more than one pin on submodule 'FS'. (LINT-33)
Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
Warning: In design 'myidct_DW02_mult_8_24_0', port 'A[7]' is not connected
to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_0', port 'TC' is not connected to
any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[31]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[30]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[29]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[28]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[27]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[26]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[25]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[24]' is not
connected to any nets. (LINT-2
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[29]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[28]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[27]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[26]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[25]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[24]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[23]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[22]' of cell 'FS'
was left unconnected. Logic 0 assumed. (LINT-0)
Warning: In design 'myidct_DW02_mult_8_24_0', a pin on submodule 'FS' is
connected to logic 1 or logic 0. (LINT-32)
 
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walala
Guest
Posts: n/a
 
      09-13-2003
Hi all,

I think I know the answer now... Thank you for you all,

-Walala
"walala" <> wrote in message
news:bjvesq$r07$...
> From the naming pattern of the "mul_8_24_x", it is easily seen that it has
> 64 multipliers...
>
> --------------------------------------------------------------------------
-
>
> Warning: In design 'myidct_DW02_mult_8_24_7', port 'A[7]' is not connected
> to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_7', port 'TC' is not connected
to
> any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[31]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[30]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[29]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[28]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[27]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[26]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[25]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_7', port 'PRODUCT[24]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'A[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', input pin 'B[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_7', a pin on submodule 'FS' is
> connected to logic 1 or logic 0. (LINT-32)
> Pin 'B[6]' is connected to logic 0.
> Pin 'B[5]' is connected to logic 0.
> Pin 'B[4]' is connected to logic 0.
> Pin 'B[3]' is connected to logic 0.
> Pin 'B[2]' is connected to logic 0.
> Pin 'B[1]' is connected to logic 0.
> Pin 'B[0]' is connected to logic 0.
> Pin 'CI' is connected to logic 0.
> Warning: In design 'myidct_DW02_mult_8_24_7', the same net is connected to
> more than one pin on submodule 'FS'. (LINT-33)
> Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
> Warning: In design 'myidct_DW02_mult_8_24_6', port 'A[7]' is not connected
> to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_6', port 'TC' is not connected
to
> any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[31]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[30]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[29]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[28]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[27]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[26]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[25]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_6', port 'PRODUCT[24]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'A[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', input pin 'B[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_6', a pin on submodule 'FS' is
> connected to logic 1 or logic 0. (LINT-32)
> Pin 'B[6]' is connected to logic 0.
> Pin 'B[5]' is connected to logic 0.
> Pin 'B[4]' is connected to logic 0.
> Pin 'B[3]' is connected to logic 0.
> Pin 'B[2]' is connected to logic 0.
> Pin 'B[1]' is connected to logic 0.
> Pin 'B[0]' is connected to logic 0.
> Pin 'CI' is connected to logic 0.
> Warning: In design 'myidct_DW02_mult_8_24_6', the same net is connected to
> more than one pin on submodule 'FS'. (LINT-33)
> Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
> Warning: In design 'myidct_DW02_mult_8_24_5', port 'A[7]' is not connected
> to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_5', port 'TC' is not connected
to
> any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[31]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[30]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[29]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[28]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[27]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[26]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[25]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_5', port 'PRODUCT[24]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'A[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', input pin 'B[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_5', a pin on submodule 'FS' is
> connected to logic 1 or logic 0. (LINT-32)
> Pin 'B[6]' is connected to logic 0.
> Pin 'B[5]' is connected to logic 0.
> Pin 'B[4]' is connected to logic 0.
> Pin 'B[3]' is connected to logic 0.
> Pin 'B[2]' is connected to logic 0.
> Pin 'B[1]' is connected to logic 0.
> Pin 'B[0]' is connected to logic 0.
> Pin 'CI' is connected to logic 0.
> Warning: In design 'myidct_DW02_mult_8_24_5', the same net is connected to
> more than one pin on submodule 'FS'. (LINT-33)
> Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
> Warning: In design 'myidct_DW02_mult_8_24_4', port 'A[7]' is not connected
> to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_4', port 'TC' is not connected
to
> any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[31]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[30]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[29]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[28]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[27]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[26]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[25]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_4', port 'PRODUCT[24]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'A[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', input pin 'B[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_4', a pin on submodule 'FS' is
> connected to logic 1 or logic 0. (LINT-32)
> Pin 'B[6]' is connected to logic 0.
> Pin 'B[5]' is connected to logic 0.
> Pin 'B[4]' is connected to logic 0.
> Pin 'B[3]' is connected to logic 0.
> Pin 'B[2]' is connected to logic 0.
> Pin 'B[1]' is connected to logic 0.
> Pin 'B[0]' is connected to logic 0.
> Pin 'CI' is connected to logic 0.
> Warning: In design 'myidct_DW02_mult_8_24_4', the same net is connected to
> more than one pin on submodule 'FS'. (LINT-33)
> Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
> Warning: In design 'myidct_DW02_mult_8_24_3', port 'A[7]' is not connected
> to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_3', port 'TC' is not connected
to
> any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[31]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[30]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[29]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[28]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[27]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[26]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[25]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_3', port 'PRODUCT[24]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'A[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', input pin 'B[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_3', a pin on submodule 'FS' is
> connected to logic 1 or logic 0. (LINT-32)
> Pin 'B[6]' is connected to logic 0.
> Pin 'B[5]' is connected to logic 0.
> Pin 'B[4]' is connected to logic 0.
> Pin 'B[3]' is connected to logic 0.
> Pin 'B[2]' is connected to logic 0.
> Pin 'B[1]' is connected to logic 0.
> Pin 'B[0]' is connected to logic 0.
> Pin 'CI' is connected to logic 0.
> Warning: In design 'myidct_DW02_mult_8_24_3', the same net is connected to
> more than one pin on submodule 'FS'. (LINT-33)
> Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
> Warning: In design 'myidct_DW02_mult_8_24_2', port 'A[7]' is not connected
> to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_2', port 'A[2]' is not connected
> to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_2', port 'TC' is not connected
to
> any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[31]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[30]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[29]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[28]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[27]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[26]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[25]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_2', port 'PRODUCT[24]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'A[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', input pin 'B[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_2', a pin on submodule 'FS' is
> connected to logic 1 or logic 0. (LINT-32)
> Pin 'B[6]' is connected to logic 0.
> Pin 'B[5]' is connected to logic 0.
> Pin 'B[4]' is connected to logic 0.
> Pin 'B[3]' is connected to logic 0.
> Pin 'B[2]' is connected to logic 0.
> Pin 'B[1]' is connected to logic 0.
> Pin 'B[0]' is connected to logic 0.
> Pin 'CI' is connected to logic 0.
> Warning: In design 'myidct_DW02_mult_8_24_2', the same net is connected to
> more than one pin on submodule 'FS'. (LINT-33)
> Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
> Warning: In design 'myidct_DW02_mult_8_24_1', port 'A[7]' is not connected
> to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_1', port 'A[4]' is not connected
> to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_1', port 'TC' is not connected
to
> any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[31]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[30]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[29]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[28]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[27]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[26]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[25]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_1', port 'PRODUCT[24]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'A[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', input pin 'B[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_1', a pin on submodule 'FS' is
> connected to logic 1 or logic 0. (LINT-32)
> Pin 'B[6]' is connected to logic 0.
> Pin 'B[5]' is connected to logic 0.
> Pin 'B[4]' is connected to logic 0.
> Pin 'B[3]' is connected to logic 0.
> Pin 'B[2]' is connected to logic 0.
> Pin 'B[1]' is connected to logic 0.
> Pin 'B[0]' is connected to logic 0.
> Pin 'CI' is connected to logic 0.
> Warning: In design 'myidct_DW02_mult_8_24_1', the same net is connected to
> more than one pin on submodule 'FS'. (LINT-33)
> Net 'lsb_0' is connected to pins 'B[0]', 'CI'.
> Warning: In design 'myidct_DW02_mult_8_24_0', port 'A[7]' is not connected
> to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_0', port 'TC' is not connected
to
> any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[31]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[30]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[29]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[28]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[27]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[26]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[25]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_0', port 'PRODUCT[24]' is not
> connected to any nets. (LINT-2
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'A[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[29]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[28]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[27]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[26]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[25]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[24]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[23]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', input pin 'B[22]' of cell
'FS'
> was left unconnected. Logic 0 assumed. (LINT-0)
> Warning: In design 'myidct_DW02_mult_8_24_0', a pin on submodule 'FS' is
> connected to logic 1 or logic 0. (LINT-32)
>
>
 
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