(walala) wrote in message news:< om>...
> Let's just imagine this design is not a chip itself, it is some module
> internal to the chip, hence I guess I can use some parallel bus... (am
> I right?)
>
If it's Ok for you, it's Ok for us...
>
> After I used your "STD_LOGIC_VECTOR(11 downto 0)" instead of the
> "INTEGER RANGE -1024 TO 1023",
>
> I got a lot of compilation error,
>
> for instance,
>
> t1<=32*x(0);
>
> where t1 is STD_LOGIC_VECTOR(16 downto 0) and x(0) is
> STD_LOGIC_VECTOR(11 downto 0);
>
> The modelsim compiler says:
>
> # ERROR: /home/min/a/xding/source/mytry.vhd(41): No feasible entries
> for infix op: "*"
> # ERROR: /home/min/a/xding/source/mytry.vhd(41): Type error resolving
> infix expression.
>
> what happened? Can you tell me?
VHDL is STRONGLY TYPED and the * operand doesn't understand
INTEGER*STD_LOGIC_VECTOR, so you have to convert the STD_LOGIC_VECTOR
to
integer. You can use:
t1<=32*CONV_INTEGER(x(0)); -- Warning: Output overflows in
multiplication
Further, we have tried to understand your program, and we have
rewritten it to this:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Renaud Pacalet: use ieee.numeric_std instead of Synopsys
std_something :
-- USE ieee.numeric_std.ALL;
-- TechCon: ..depending on your tool version..
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
PACKAGE MYTYPES IS
-- TechCon: Good Design Practice: Use STD_LOGIC(_VECTOR) in the
interfaces:
SUBTYPE INPUT_WORD IS STD_LOGIC_VECTOR(11 downto 0); -- -1024 TO
1023;
SUBTYPE OUTPUT_BYTE IS STD_LOGIC_VECTOR(7 downto 0); -- -128 TO
127;
SUBTYPE TEMP_BYTE IS STD_LOGIC_VECTOR(8 downto 0); -- -256 TO 255;
SUBTYPE INTERNAL_WORD IS INTEGER RANGE -65536 TO 65535;
TYPE INPUT_WORD_ARRAY IS ARRAY(0 TO 5) OF INPUT_WORD;
TYPE OUTPUT_BYTE_ARRAY IS ARRAY(0 TO 7) OF OUTPUT_BYTE;
TYPE TEMP_BYTE_ARRAY IS ARRAY(0 TO 7) OF TEMP_BYTE;
END PACKAGE MYTYPES;
USE work.mytypes.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Renaud Pacalet: use ieee.numeric_std instead of Synopsys
std_something :
-- USE ieee.numeric_std.ALL;
-- TechCon: ..depending on your tool version..
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY mytry IS
PORT(-- TechCon: Use an Asynchronous Reset:
rst : IN std_logic;
clk : IN std_logic;
-- TechCon: Good Design Practice: Use STD_LOGIC(_VECTOR) in
the interfaces:
x : IN INPUT_WORD_ARRAY;
y : OUT OUTPUT_BYTE_ARRAY);
END mytry;
ARCHITECTURE flex OF mytry IS
SIGNAL t1, t2, t3, t4, t5, t6, t7: INTERNAL_WORD;
BEGIN
-- TechCon: Convert from STD_LOGIC(_VECTOR) to integer before
MULTIPLICATION
t1<=32*CONV_INTEGER(x(0)); -- Warning: Output overflows in
multiplication
t2<=44*CONV_INTEGER(x(1));
t3<=38*CONV_INTEGER(x(2));
t4<=25*CONV_INTEGER(x(3));
t5<= 9*CONV_INTEGER(x(4));
t6<= 7*CONV_INTEGER(x(5));
t7<= 3*CONV_INTEGER(x(1));
-- Renaud Pacalet: Your process should be sensitive to clock and
async reset only:
p1: PROCESS(clk, rst)
VARIABLE count: INTEGER RANGE 0 TO 8;
-- Renaud Pacalet: You don't need to declare a variable I for
your loop index.
-- VARIABLE i: INTEGER RANGE 0 TO 7;
VARIABLE temp1: INTERNAL_WORD;
VARIABLE temp: TEMP_BYTE_ARRAY;
BEGIN
if rst = '0' then
count := 0;
-- TechCon: Use elsif instead of "end if; if "
elsif rising_edge(clk) then
case count is
when 0 =>
temp1:=t1+t2;
when 1 =>
temp1:=t1+t3;
when 2 =>
temp1:=t1+t4;
when 3 =>
temp1:=t1+t5;
when 4 =>
temp1:=t1-t5;
when 5 =>
temp1:=t1-t4;
when 6 =>
temp1:=t1-t3;
when 7 =>
temp1:=t1-t2;
when others => null;
end case;
count:=count+1;
if count=8 then
count:=0;
end if;
temp(0):=CONV_STD_LOGIC_VECTOR(temp1+t6, 17)(15 downto 7);
temp(1):=CONV_STD_LOGIC_VECTOR(temp1+t7, 17)(15 downto 7);
temp(2):=CONV_STD_LOGIC_VECTOR(temp1-t7, 17)(15 downto 7);
temp(3):=CONV_STD_LOGIC_VECTOR(temp1-t6, 17)(15 downto 7);
temp(4):=CONV_STD_LOGIC_VECTOR(temp1-t6, 17)(15 downto 7);
temp(5):=CONV_STD_LOGIC_VECTOR(temp1-t7, 17)(15 downto 7);
temp(6):=CONV_STD_LOGIC_VECTOR(temp1+t7, 17)(15 downto 7);
temp(7):=CONV_STD_LOGIC_VECTOR(temp1+t6, 17)(15 downto 7);
for i in 0 to 7 loop
if temp(i)(0)='1' then
Y(i)<=temp(i)(8 downto 1) + 1;
else
Y(i)<=temp(i)(8 downto 1);
end if;
end loop;
end if;
END PROCESS;
END flex;
We hope that helps you further.
Send us and EMail to
if you need more
assistance.
TechCon.
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