Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > what are the possible reasons that successful pre-synthesis simulation + successful synthesis = failed post-synthes

Reply
Thread Tools

what are the possible reasons that successful pre-synthesis simulation + successful synthesis = failed post-synthes

 
 
walala
Guest
Posts: n/a
 
      09-07-2003
Dear all,

I have run the pre-synthesis successfully using Modelsim successfully, and
then I do a Synopsys DC synthesis successfully(only have some warnings, no
errors), but when it came to post-synthesis using Modelsim, the outputs
became "XXXXXXXXXXXXX"(no values); some internal nodes have "0", some
internal nodes have "1", and the other internal nodes have "X"... but the
internal nodes were stuck with their values: the "0"s were always "0", the
"1"s were always "1", the "X"s were always "X"...

Worth noting is that I follow the same workflow for some very small designs,
it worked perfectly... but now it failed for medium-big size design...

I feel the errors are so systemetic, which may be caused by some hidden
tricks(for large size design) in Synopsys DC that I did not know...

Can anybody help me out of this swamp?

Thanks:

--------------------------------------------------------------
My script file:

$SYNOPSYS/sparcOS5/syn/bin/dc_shell-t <<!
redirect myidct.log {
analyze -format vhdl -lib WORK {myidct.vhd}
elaborate myidct -arch "flex" -lib WORK -update
ungroup -all -flatten
create_clock "clk" -name "clk" -period 10
compile -map_effort medium
current_design .
report_timing -path full -delay max -max_paths 1 -nworst 1 >
reports/\$current_d
esign.rep
report_area >> reports/\$current_design.rep
change_names -rules vhdl
write -format vhdl -hierarchy -output "mapped/\$current_design.vhd"
write -format verilog -hierarchy -output "mapped/\$current_design.v"
plot -hierarchy -output "schematic/\$current_design.ps"
echo "\nScript Done\n"
echo "\nChecking Design\n"
check_design
}
!

---------------------------------------------------------




 
Reply With Quote
 
 
 
 
Ralf Hildebrandt
Guest
Posts: n/a
 
      09-07-2003
Hi walala!


> I have run the pre-synthesis successfully using Modelsim successfully, and
> then I do a Synopsys DC synthesis successfully(only have some warnings, no
> errors), but when it came to post-synthesis using Modelsim, the outputs
> became "XXXXXXXXXXXXX"(no values); some internal nodes have "0", ...


Split your design into smaller components. Run synthesis step-by-step,
only one new synthesized components at a time.

Think about hazards (glitches). Do have latches within your design? - If
yes, think carefully about run-time - problems.

And last of all: Don't "program" a chip with VHDL - chips have to be
designed / described. Think about every line of code, what it could be
synthesized to.

Ralf

 
Reply With Quote
 
 
 
 
walala
Guest
Posts: n/a
 
      09-08-2003
Hi Ralf,

Thank you very much for your answer!

> Split your design into smaller components. Run synthesis step-by-step,
> only one new synthesized components at a time.


Good idea! I will try out!


> Think about hazards (glitches). Do have latches within your design? - If
> yes, think carefully about run-time - problems.
>
> And last of all: Don't "program" a chip with VHDL - chips have to be
> designed / described. Think about every line of code, what it could be
> synthesized to.


That's my problem. I really have no idea what each line of code will be
synthesized to;

sometimes relocating some sentences will change the whole hardware.

I guess the code was synthesized to the hardware I did not expect...(see my
another post -- newbie question about synthesizable VHDL code)

Are there any books/online resources can help me familiar with which code
synthesize to what hardware? or this is just a purely experience based
learning process that only the old veteran will know the tricks?

> Ralf
>


-Walala


 
Reply With Quote
 
Renaud Pacalet
Guest
Posts: n/a
 
      09-08-2003
walala wrote:
> Dear all,
>
> I have run the pre-synthesis successfully using Modelsim successfully, and
> then I do a Synopsys DC synthesis successfully(only have some warnings, no
> errors), but when it came to post-synthesis using Modelsim, the outputs
> became "XXXXXXXXXXXXX"(no values); some internal nodes have "0", some
> internal nodes have "1", and the other internal nodes have "X"... but the
> internal nodes were stuck with their values: the "0"s were always "0", the
> "1"s were always "1", the "X"s were always "X"...
>
> Worth noting is that I follow the same workflow for some very small designs,
> it worked perfectly... but now it failed for medium-big size design...
>
> I feel the errors are so systemetic, which may be caused by some hidden
> tricks(for large size design) in Synopsys DC that I did not know...
>
> Can anybody help me out of this swamp?


A problem of pre-post synthesis simulations mismatches is usually not a
synthesis script problem. It usually comes from a pre-synthesis model
describing something that cannot be implemented on the target
technology. Most synthesizers raise warnings when they encounter
unsupported or partially supported statements. Did you carefully read dc
warnings. If yes post your pre-synthesis VHDL and we'll tell you what's
wrong.

Regards,
--
Renaud Pacalet, ENST, 46 rue Barrault 75634 Paris Cedex 13
###### Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 ######
# Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ #

 
Reply With Quote
 
Ralf Hildebrandt
Guest
Posts: n/a
 
      09-08-2003
Hi walala!


>>And last of all: Don't "program" a chip with VHDL - chips have to be
>>designed / described. Think about every line of code, what it could be
>>synthesized to.


> That's my problem. I really have no idea what each line of code will be
> synthesized to;



A very small list:
http://groups.google.de/groups?q=Ral...ncis.de&rnum=1



> Are there any books/online resources can help me familiar with which code
> synthesize to what hardware? or this is just a purely experience based
> learning process that only the old veteran will know the tricks?


Every HDL book should tell you this stuff. The problem is, that most
books will not recommend a single template for every problem, because
nobody is perferct and it is the skill of the designer to build _new_
efficient descriptions.


Ralf

 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Simulation vs Synthesis ALuPin@web.de VHDL 14 02-21-2006 10:15 AM
long counters in simulation and synthesis Eli Bendersky VHDL 7 10-27-2004 07:22 AM
25 Reasons to Aviod the SD-10 (was 15 Reasons to Aviod the SD-10) Steven M. Scharf Digital Photography 823 07-02-2004 12:55 PM
Simulation is OK but problem with synthesis Andy VHDL 5 10-22-2003 06:24 AM
SOS! newbie question about synthesizable VHDL : synthesis run successfully but post-synthesis failed... walala VHDL 4 09-09-2003 08:41 AM



Advertisments