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Prioritising nets

 
 
Willem Oosthuizen
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      09-03-2003
Suppose I have an entity with inputs a,b,c,and d; all std_logic. and an
output q. The whole entity is combinatorial.

I want to mask the effect of inputs b,c and d with a.

Inside my code:

q <= '0' when a = '0' else q_p.

-- where q_p if a signal derived from b,c and d.

I want the mask a to go through the minimum levels of logic. The synthesis
tool tries to make the level of logic have equal for all inputs a,b,c and d.

How do I code the VHDL to get this right?. I have tried everything.

Please help.

Willem





 
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Renaud Pacalet
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      09-03-2003
Willem Oosthuizen wrote:
> Suppose I have an entity with inputs a,b,c,and d; all std_logic. and an
> output q. The whole entity is combinatorial.
>
> I want to mask the effect of inputs b,c and d with a.
>
> Inside my code:
>
> q <= '0' when a = '0' else q_p.
>
> -- where q_p if a signal derived from b,c and d.
>
> I want the mask a to go through the minimum levels of logic. The synthesis
> tool tries to make the level of logic have equal for all inputs a,b,c and d.
>
> How do I code the VHDL to get this right?. I have tried everything.


Component instanciation and "don't touch" options are a good and simple
way of controlling a synthesizer. So you could try to encapsulate your
b,c,d stuff in a sub-component.

Regards,
--
Renaud Pacalet, ENST, 46 rue Barrault 75634 Paris Cedex 13
###### Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 ######
# Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ #

 
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Willem Oosthuizen
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      09-03-2003

"Renaud Pacalet" <(E-Mail Removed) > wrote
in message news:bj4dv8$15eu$(E-Mail Removed)...
> Willem Oosthuizen wrote:
> > Suppose I have an entity with inputs a,b,c,and d; all std_logic. and an
> > output q. The whole entity is combinatorial.
> >
> > I want to mask the effect of inputs b,c and d with a.
> >
> > Inside my code:
> >
> > q <= '0' when a = '0' else q_p.
> >
> > -- where q_p if a signal derived from b,c and d.
> >
> > I want the mask a to go through the minimum levels of logic. The

synthesis
> > tool tries to make the level of logic have equal for all inputs a,b,c

and d.
> >
> > How do I code the VHDL to get this right?. I have tried everything.

>
> Component instanciation and "don't touch" options are a good and simple
> way of controlling a synthesizer. So you could try to encapsulate your
> b,c,d stuff in a sub-component.
>
> Regards,
> --
> Renaud Pacalet, ENST, 46 rue Barrault 75634 Paris Cedex 13
> ###### Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 ######
> # Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ #
>

I have tried this and it works. Thank you. It is unfortunately not allways
easy to do.
Breaking designs up in small junks makes the code unreadable. I sometimes
wonder if schematics isn't a better option...



 
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Renaud Pacalet
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      09-03-2003
Willem Oosthuizen wrote:

> I have tried this and it works. Thank you. It is unfortunately not allways
> easy to do.
> Breaking designs up in small junks makes the code unreadable. I sometimes
> wonder if schematics isn't a better option...


Well, when you know exactly what netlist you need, schematics and VHDL
are almost equivalent. Almost only because one is portable and the other
is sometimes easier to read.

Regards,
--
Renaud Pacalet, ENST, 46 rue Barrault 75634 Paris Cedex 13
###### Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 ######
# Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ #

 
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