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Coding style to prioritize certain inputs

 
 
Willem Oosthuizen
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      09-02-2003
Is the rules of thumb to prioritise certain inputs to go through less logic
before flip-flops that other nets in VHDL?

I can not found any definate pattern if there is no elsif structures. What
to do?

I use Synplify.



 
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Willem Oosthuizen
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      09-02-2003
"Willem Oosthuizen" <(E-Mail Removed)> wrote in message
news:bj1vh8$htg$(E-Mail Removed)...
> Is the rules of thumb to prioritise certain inputs to go through less

logic
> before flip-flops that other nets in VHDL?
>
> I can not found any definate pattern if there is no elsif structures. What
> to do?
>
> I use Synplify.
>
>
>


Suppose I want to write this code, and we assume a 4 input look-up table
target technology. a_Const to k_const is constants I want to prioritize
inputs a,b and c.
How do I re-write the code to give this to me? The synthesizer only
prioritizes "a".

process (a,b,c,d,e,f,g,h,i,j,k)
begin
q_p <= '0';
if a = a_const then
if b = b_const then
if c = c_const then
if d = d_const then
if e = e_const then
if f = f_const then
if g = g_const then
if h = h_const then
if i = i_const then
if j = j_const then
if k = k_const then
q_p <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;

process(aclr_l,clk)
begin
if aclr_l = '0' then
q<= '0';
elsif clk'event and clk = '1' then
q<= q_p;
end if;
end process;
END test;




 
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Egbert Molenkamp
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Posts: n/a
 
      09-02-2003

"Willem Oosthuizen" <(E-Mail Removed)> schreef in bericht
news:bj23jr$jic$(E-Mail Removed)...
> Suppose I want to write this code, and we assume a 4 input look-up table
> target technology. a_Const to k_const is constants I want to prioritize
> inputs a,b and c.
> How do I re-write the code to give this to me? The synthesizer only
> prioritizes "a".
>


There is an ELSIF see next pice of code:

process (a,b,c,d,e,f,g,h,i,j,k)
begin
q_p <= '0';
if a = a_const then
elsif b = b_const then
elsif c = c_const then
elsif d = d_const then
elsif e = e_const then
elsif f = f_const then
elsif g = g_const then
elsif h = h_const then
elsif i = i_const then
elsif j = j_const then
elsif k = k_const then
q_p <= '1';
end if;
end process;

> The synthesizer only prioritizes "a".


In this example, I think, the behavior is the same if the conditions are
checked in any order.
This property can be used by a synthesis tool to shorten a long chain (=
delay) and may be a
little more hardware is needed. I think Synplify has some switches you can
use to emphasize
speed or area.

Egbert Molenkamp




 
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Willem Oosthuizen
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Posts: n/a
 
      09-02-2003

"Egbert Molenkamp" <(E-Mail Removed)> wrote in message
news:bj25rb$7h$(E-Mail Removed)...
>
> "Willem Oosthuizen" <(E-Mail Removed)> schreef in bericht
> news:bj23jr$jic$(E-Mail Removed)...
> > Suppose I want to write this code, and we assume a 4 input look-up table
> > target technology. a_Const to k_const is constants I want to prioritize
> > inputs a,b and c.
> > How do I re-write the code to give this to me? The synthesizer only
> > prioritizes "a".
> >

>
> There is an ELSIF see next pice of code:
>
> process (a,b,c,d,e,f,g,h,i,j,k)
> begin
> q_p <= '0';
> if a = a_const then
> elsif b = b_const then
> elsif c = c_const then
> elsif d = d_const then
> elsif e = e_const then
> elsif f = f_const then
> elsif g = g_const then
> elsif h = h_const then
> elsif i = i_const then
> elsif j = j_const then
> elsif k = k_const then
> q_p <= '1';
> end if;
> end process;
>
> > The synthesizer only prioritizes "a".

>
> In this example, I think, the behavior is the same if the conditions are
> checked in any order.
> This property can be used by a synthesis tool to shorten a long chain (=
> delay) and may be a
> little more hardware is needed. I think Synplify has some switches you can
> use to emphasize
> speed or area.
>
> Egbert Molenkamp
>
>
>
>

The problem I am trying to solve is external setup time. Just selecting
Speed will try and optimize register to register delays. Not what I am
after.



 
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eadgbe
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Posts: n/a
 
      09-04-2003
You need to tell your synthesis tool what the arrival time of "a" is so that
it will understand to prioritize this for you. I recommend that you leave
your code alone.

Bob


"Willem Oosthuizen" <(E-Mail Removed)> wrote in message news:bj26pk$le4$(E-Mail Removed)...
>
> "Egbert Molenkamp" <(E-Mail Removed)> wrote in message
> news:bj25rb$7h$(E-Mail Removed)...
> >
> > "Willem Oosthuizen" <(E-Mail Removed)> schreef in bericht
> > news:bj23jr$jic$(E-Mail Removed)...
> > > Suppose I want to write this code, and we assume a 4 input look-up table
> > > target technology. a_Const to k_const is constants I want to prioritize
> > > inputs a,b and c.
> > > How do I re-write the code to give this to me? The synthesizer only
> > > prioritizes "a".
> > >

> >
> > There is an ELSIF see next pice of code:
> >
> > process (a,b,c,d,e,f,g,h,i,j,k)
> > begin
> > q_p <= '0';
> > if a = a_const then
> > elsif b = b_const then
> > elsif c = c_const then
> > elsif d = d_const then
> > elsif e = e_const then
> > elsif f = f_const then
> > elsif g = g_const then
> > elsif h = h_const then
> > elsif i = i_const then
> > elsif j = j_const then
> > elsif k = k_const then
> > q_p <= '1';
> > end if;
> > end process;
> >
> > > The synthesizer only prioritizes "a".

> >
> > In this example, I think, the behavior is the same if the conditions are
> > checked in any order.
> > This property can be used by a synthesis tool to shorten a long chain (=
> > delay) and may be a
> > little more hardware is needed. I think Synplify has some switches you can
> > use to emphasize
> > speed or area.
> >
> > Egbert Molenkamp
> >
> >
> >
> >

> The problem I am trying to solve is external setup time. Just selecting
> Speed will try and optimize register to register delays. Not what I am
> after.
>
>
>



 
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Mike Treseler
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      09-04-2003
eadgbe wrote:
> You need to tell your synthesis tool what the arrival time of "a" is so that
> it will understand to prioritize this for you. I recommend that you leave
> your code alone.


> Bob


Yes. Either make it a place&route constraint
or register the inputs.

-- Mike Treseler

 
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