In article <(EMail Removed) >,
arkaitz <(EMail Removed)> wrote:
>Hi,
>
>I have a doubt about the result of a VHDL code when simulating.
>
>I'd like to know result of a Process statement when two or more events
>on the signals of the sensitivity list happen simultaneously.
>
>Here's a little example:
>
>PROCESS (a, b, c)
>BEGIN
>
> if (a = '1') then
> result <= a;
> elsif (b = '0') then
> result <= b;
> elsif (c'event) then
> result <= c;
> end if;
>
>END PROCESS;
>
>So, imagine an hypotetical case where ocurs an event on the three
>signal a, b and c. Which would be the value of "result"?
Depends on the values of a/b/c.
There is only one driver for result in this process  the process itself
contributes the driver.
If there are concurrent events, then this is treated the same way as
single events  the process is triggered, and it computes a value for
result based on the logic.
Note, however, that this code is not recommended. Due to delta delays,
the events on a/b/c may not actually truly be concurrent, but may arrive
in any order, even though they appear to happen at the same simulator time.
Recall that each tick of simulator time is further subdivided into delta,
as many as required to resolve all activity during that tick.
In this case, that last c'event claude can be ordersensitive.
