Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Switch level simulation package

Reply
Thread Tools

Switch level simulation package

 
 
Mike Bolotski
Guest
Posts: n/a
 
      08-18-2003
Hello.

I see this question coming up once a year or so, but I haven't seen a
general enough solution.

I have a VHDL-based, transistor-level netlist created by ViewDraw. I'd
like to simulate it in VHDL for a variety of reasons.

Is there a decent model for NFETs and PFETs that handles bidirectional
switches, capacitive nodes (for dynamic logic), etc?

There are tantalizing possibilities in Ashenden's book, but I'd rather
not reinvent the wheel. All articles that I'm able to read give a
one-page overview but don't provide the full details for the mos
package.

Help?

PS. Ben Cohen's models are pretty, but have a failure mode...
 
Reply With Quote
 
 
 
 
VhdlCohen
Guest
Posts: n/a
 
      08-18-2003
>I see this question coming up once a year or so, but I haven't seen a
>general enough solution.
>
>I have a VHDL-based, transistor-level netlist created by ViewDraw. I'd
>like to simulate it in VHDL for a variety of reasons.
>
>Is there a decent model for NFETs and PFETs that handles bidirectional
>switches, capacitive nodes (for dynamic logic), etc?
>
>There are tantalizing possibilities in Ashenden's book, but I'd rather
>not reinvent the wheel. All articles that I'm able to read give a
>one-page overview but don't provide the full details for the mos
>package.
>
>Help?
>
>PS. Ben Cohen's models are pretty, but have a failure mode.


Your best bet is to use Verilog if you can get the netlist to be created by
your tool.
VHDL is weak on switch level modeling.
By the way, mixed mode simulation with VHDL models for everything and Verilog
models for the switches does NOT work im either ModelSim or NcSim.
It might be a lot of work, but you could write a script or code to translate
VHDL netlist to Verilog.
Best of luck!!!
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ http://www.velocityreviews.com/forums/(E-Mail Removed)
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
gate level simulation jasperng VHDL 0 12-09-2008 06:47 AM
Top level output keeps showing undefined XXX in simulation Jaco Naude VHDL 5 11-27-2008 08:12 PM
Problem with post-route simulation / timing simulation jasperng VHDL 0 11-27-2008 06:23 AM
c is a low-level language or neither low level nor high level language pabbu C Programming 8 11-07-2005 03:05 PM
VM-level date simulation Andrea Marchesani Java 3 01-02-2004 11:36 AM



Advertisments