Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Delay of control signals

Thread Tools

Delay of control signals

Ingmar Seifert
Posts: n/a

As desribed some threads above I have a multplier an adder and a
registerbank in a row.
I furtermore have a FSM that generates controlsignals for the
operand-multiplexers of each unit.

To control one run through this row I have to set the mul-control-signal
at first, one clock later the add-control-signal and two clock cycles
later the control-signal that chooses the location to store the result
of the run.

At the moment I set in state1 the mul-control-signal in state2 the
add-control-signal and in state3 the capture-control-signal.

Is it a common way to set all control-signals in one state and delay
them (with D-FlipFlops) by one and two clock cycles?

Thanks in advance.
Ingmar Seifert

Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
wireless zero config not displaying any signals, if any third partywireless client takes control and gives control back to wzc Naresh Samba Wireless Networking 6 06-09-2009 06:52 PM
Calculating propagation delay & transmission delay Stone Cisco 1 09-27-2006 06:26 PM
Question to resolved signals, transport delay VHDL 6 05-09-2006 10:43 AM
help with concurrency control (threads/processes & signals) Sori Schwimmer Python 1 10-27-2005 05:37 PM
control-c and threads, signals in 2.3 causing all sorts of issues Srikanth Mandava Python 1 02-19-2004 12:41 PM