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Array (Newbie)

 
 
smu
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      08-18-2003
Hello,

I search the good syntax for do anything like

architecture ... of ... is
signal s : array(0 to 2 of std_logic_vector(15 downto 0);
begin
process (clk)
begin
s( 1)(15 downto 0) <= s( 0)(15 downto 0);
s( 2)(15 downto 0) <= s( 1)(15 downto 0);
....
end;
end;

That is the good way to code the signal declaration ?

In the final version, I use GENERATE to replace the current process coding.

Thank you in advance

smu


 
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smu
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Posts: n/a
 
      08-18-2003
Thank you very much

"Egbert Molenkamp" <(E-Mail Removed)> a écrit dans le
message de news:bhqhkp$ck7$(E-Mail Removed)...
> I think you like to describe a shift register with 29 stages, each stage

16
> bits.
>
> Your signal declaration is not correct. First you have to declare a type,
> > signal s : array(0 to 2 of std_logic_vector(15 downto 0);

> becomes someting like:
> type s_type is array(0 to 2 of std_logic_vector(15 downto 0);
> signal s : s_type
>
> Then writing 28 times almost the same, e.g.
> > s( 1)(15 downto 0) <= s( 0)(15 downto 0);
> > s( 2)(15 downto 0) <= s( 1)(15 downto 0);

> You could use a loop statement (I don't think a generate statement is
> needed,
> althoug possible).
> Finally with a little addition you can make a generic solution. Eg. the
> depth of the pipeline and the data_with. These generics are included in

the
> entity part. When you instantiate this entity you can use different values
> for the generic length and data_width.
>
> Here an generic solution:
>
> library ieee;
> use ieee.std_logic_1164.all;
> entity shift is
> generic (length : positive := 5; data_width : positive := 3 );
> port (reset, clk : in std_logic;
> di : in std_logic_vector(data_width-1 downto 0);
> do : out std_logic_vector(data_width-1 downto 0)
> );
> end shift;
>
> architecture demo of shift is
> type s_type is array(natural range <>) of std_logic_vector(data_width-1
> downto 0);
> signal s : s_type(length-1 downto 0);
> begin
> process (reset,clk)
> begin
> if reset='0' then
> s <= (others => (others => '0'));
> elsif rising_edge(clk) then
> s(0) <= di;
> for i in s'length-1 downto 1 loop
> s(i) <= s(i-1);
> end loop;
> end if;
> end process;
> do <=s(length-1);
> end;
>
> Egbert Molenkamp
>
>
> "smu" <(E-Mail Removed)> wrote in message
> news:3f407fea$0$1142$(E-Mail Removed)...
> > Hello,
> >
> > I search the good syntax for do anything like
> >
> > architecture ... of ... is
> > signal s : array(0 to 2 of std_logic_vector(15 downto 0);
> > begin
> > process (clk)
> > begin
> > s( 1)(15 downto 0) <= s( 0)(15 downto 0);
> > s( 2)(15 downto 0) <= s( 1)(15 downto 0);
> > ....
> > end;
> > end;
> >
> > That is the good way to code the signal declaration ?
> >
> > In the final version, I use GENERATE to replace the current process

> coding.
> >
> > Thank you in advance
> >
> > smu
> >
> >

>
>



 
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Egbert Molenkamp
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Posts: n/a
 
      08-19-2003
Almost, I think you mean:
s(s'length-1 downto 1) <= s(s'length-2 downto 0);

However I used a generic 'length':
generic (length : positive := 5;

What happens if length is 1. Only one clock delay.
In that case the above statement becomes:
s(0 downto 1) <= s(-1 downto 0);

"0 downto 1" is a null array; no problem.
"-1 downto 0" is also a null array
In this case s(-1 downto 0) is interesting. It is
a null array AND (-1) is out of the index range
that is allowed in the std_logic_vector.

At least my synthesis tool, and I know from other
synthesis tools too, do not like it and complains
with "index out of range". Does you tool
support it?

My simulator has no problems and showed the
behaviour I expected.

My interpretation of the VHDL-LRM is that
only if it is not a null range the index range is
checked (in that case your solution should work
also for length is 1). But since you sometimes
need to synthesize stuff .. be careful.

Egbert Molenkamp

"MK" <(E-Mail Removed)> wrote in message
news:bhshgl$283$(E-Mail Removed)...
> for i in s'length-1 downto 1 loop
> s(i) <= s(i-1);
> end loop;
>
> This can be expressed in the other way:
>
> s(s'length downto 1) <= s(s'length-1 downto 0);
>
> or:
>
> s <= s(s'length-1 downto 0) & s(0); -- s(0) will be unchanged
>
> regards,
> MK.
>
> "Egbert Molenkamp" <(E-Mail Removed)> wrote in message
> news:bhqhkp$ck7$(E-Mail Removed)...
> > I think you like to describe a shift register with 29 stages, each stage

> 16
> > bits.
> >
> > Your signal declaration is not correct. First you have to declare a

type,
> > > signal s : array(0 to 2 of std_logic_vector(15 downto 0);

> > becomes someting like:
> > type s_type is array(0 to 2 of std_logic_vector(15 downto 0);
> > signal s : s_type
> >
> > Then writing 28 times almost the same, e.g.
> > > s( 1)(15 downto 0) <= s( 0)(15 downto 0);
> > > s( 2)(15 downto 0) <= s( 1)(15 downto 0);

> > You could use a loop statement (I don't think a generate statement is
> > needed,
> > althoug possible).
> > Finally with a little addition you can make a generic solution. Eg. the
> > depth of the pipeline and the data_with. These generics are included in

> the
> > entity part. When you instantiate this entity you can use different

values
> > for the generic length and data_width.
> >
> > Here an generic solution:
> >
> > library ieee;
> > use ieee.std_logic_1164.all;
> > entity shift is
> > generic (length : positive := 5; data_width : positive := 3 );
> > port (reset, clk : in std_logic;
> > di : in std_logic_vector(data_width-1 downto 0);
> > do : out std_logic_vector(data_width-1 downto 0)
> > );
> > end shift;
> >
> > architecture demo of shift is
> > type s_type is array(natural range <>) of

std_logic_vector(data_width-1
> > downto 0);
> > signal s : s_type(length-1 downto 0);
> > begin
> > process (reset,clk)
> > begin
> > if reset='0' then
> > s <= (others => (others => '0'));
> > elsif rising_edge(clk) then
> > s(0) <= di;
> > for i in s'length-1 downto 1 loop
> > s(i) <= s(i-1);
> > end loop;
> > end if;
> > end process;
> > do <=s(length-1);
> > end;
> >
> > Egbert Molenkamp
> >
> >
> > "smu" <(E-Mail Removed)> wrote in message
> > news:3f407fea$0$1142$(E-Mail Removed)...
> > > Hello,
> > >
> > > I search the good syntax for do anything like
> > >
> > > architecture ... of ... is
> > > signal s : array(0 to 2 of std_logic_vector(15 downto 0);
> > > begin
> > > process (clk)
> > > begin
> > > s( 1)(15 downto 0) <= s( 0)(15 downto 0);
> > > s( 2)(15 downto 0) <= s( 1)(15 downto 0);
> > > ....
> > > end;
> > > end;
> > >
> > > That is the good way to code the signal declaration ?
> > >
> > > In the final version, I use GENERATE to replace the current process

> > coding.
> > >
> > > Thank you in advance
> > >
> > > smu
> > >
> > >

> >
> >

>
>



 
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