Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > VHDL for FPGA VME Slave

Reply
Thread Tools

VHDL for FPGA VME Slave

 
 
Colin Jackson
Guest
Posts: n/a
 
      08-15-2003
I'm working on a FPGA that is to have a few R/W registers on a VME bus.

Anybody have some VHDL code they would like to share?

If I use your ideas then your name will forever be in lights!

Thanks!


 
Reply With Quote
 
 
 
 
Jonathan Bromley
Guest
Posts: n/a
 
      08-18-2003
"Colin Jackson" <jacksoncolin@fake_yahoo.com> wrote in
message news(E-Mail Removed)...
> I'm working on a FPGA that is to have a few R/W registers on a VME bus.
>
> Anybody have some VHDL code they would like to share?
>
> If I use your ideas then your name will forever be in lights!


Be very, very afraid.

VME was defined as an *asynchronous* protocol to keep it
independent of any CPU's clock. Consequently, any VME
interface needs to be sensitive to EDGES on several different
strobe signals (*DS0, *DS1, *AS and several others). I think
you can do a reasonable job if you are prepared to oversample
all the strobes with a clock of about 80MHz or faster, but
a direct (asynch) implementation in FPGA would be horrible.

Once you've coped with that asynch-strobes nonsense, the main
remaining problem is performance. Given that you're only
accessing a few registers, speed may not be a major problem.
If this is so, the rest of the task is comparatively easy -
just a matter of reading the fine print carefully, so that
you don't get confused about address modifiers, word
widths and burst transfers.

Finally, be careful about electrical specs. VME was defined
around a particular set of LSTTL devices (74LS641-1 bidi
buffers, and a few others). Output drivers need to be able
to sink 64mA, and be 5V-tolerant, to meet the specs. 74F543
bidi latch/buffer chips are your friends here, if you can
still get 'em.

Enjoy!
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: http://www.velocityreviews.com/forums/(E-Mail Removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



 
Reply With Quote
 
 
 
 
Tullio Grassi
Guest
Posts: n/a
 
      08-19-2003
Have a look to :

http://schwick.home.cern.ch/schwick/...ndex-long.html

It seem a well organized job (not mine).



On Fri, 15 Aug 2003, Colin Jackson wrote:

> I'm working on a FPGA that is to have a few R/W registers on a VME bus.
>
> Anybody have some VHDL code they would like to share?
>
> If I use your ideas then your name will forever be in lights!
>
> Thanks!
>
>
>


 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Re: FPGA BOARD FOR NEWBIE TO FPGA Oliver Mattos VHDL 0 02-02-2011 10:33 PM
FPGA BOARD FOR NEWBIE TO FPGA TheRightInfo VHDL 1 02-02-2011 11:19 AM
FPGA Central eNewsletter - LinkedIn, Write Articles, Post FREE Jobs,FPGA for Mobiles Vikram VHDL 0 07-24-2008 07:37 PM
VHDL-2002 vs VHDL-93 vs VHDL-87? afd VHDL 1 03-23-2007 09:33 AM
VME VHDL bench smu VHDL 7 11-23-2005 05:35 PM



Advertisments