VHDL Packages

If you have two packages being used in a top-level design, can you
have the same constants/dataTypes be defined in each of the packages ?

Sandeep

"Sandeep" <> wrote in message
news: om...
> If you have two packages being used in a top-level design, can you
> have the same constants/dataTypes be defined in each of the packages ?

Yes (but in practice No)

PACKAGE x IS
CONSTANT c : integer := 5;
END x;

PACKAGE y IS
CONSTANT c : integer := 10;
END y;

USE work.x.all;
USE work.y.all;
ENTITY use_package IS
PORT (r : in integer := c
);
END use_package;

In the example above the constant c is declared in both package.
Which c is to be used in the port declaration for signal r?
Your tool will probably complain; there are two c's possible.
Solutions:
- use only ONE package (remove a USE clause), or
- make explicit which constant c is to be use, i.e.
ENTITY use_package IS
PORT (r : in integer := work.x.c
);
assumed is that the package is compiled in library work, and
you want the constant c from package x.

Egbert Molenkamp

Egbert Molenkamp