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Hello Sarah,

> So, i need to keep the signal : start_tx longer until the rising endge of
> Uart_clcok.
> Does anyboday know how to slove this problem? Which logic should be
> used?

It's a 3 step approach:

1. Stretch the start_tx signal such that it is longer than the clock pulse
of the UART clock including clock skew. A simple counter to turn the
start_tx signal on and off should do the trick. It's no problem if the
start_tx pulse is a bit longer than it needs to be. Too short however will
cause problems.
2. Clock the start_tx to the UART clock using 3 FFs to avoid meta-stability.
3. Perform a positive edge detection on the output of the 2nd and 3rd FF
using the UART clock.


For step 2 and 3:

PROCESS
BEGIN
WAIT UNTIL uart_clk = '1';
uart_start_tx <= start_tx; -- 1st FF
uart_start_tx_1d <= uart_start_tx; -- 2nd FF
uart_start_tx_2d <= uart_start_tx_1d; -- 3rd FF
-- rising edge detection
IF uart_start_tx_1d = '1' AND uart_start_tx_2d = '0' THEN
-- start your transmission here
END IF;
END PROCESS;


Hope this helps,

Pieter Hulshoff