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Re: vhdl UART

 
 
Mike Treseler
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      08-08-2003
SneakerNet wrote:

> The receive module of the uart has these I/Os:
> clock: input
> baudclock: input
> RxD: input
> Data_FromPC[7..0]: output




That would be Data_To_PC




> RxComplete: output
>
> The I/O's are self-explanatory.
> Now how can i use the RxComplete signal to implement the buffer? Help. Any
> info/advice appreciated.





1 8 8
RxD]---[UART]---/--[FIFO]--/---[Data_To_PC



-- Mike Treseler

 
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SneakerNet
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      08-10-2003
Hi Mike..

I would like to point out that this is a receiver module (Rx) so what I
wrote was correct. It is Data_FromPc[7..0] as it is a uart module that
receives data from PC and sends it to other modules within FPGA. I don't
know how you got the idea that it is Data_To_PC!.

Anyway I have no idea what your reply means. Can you pls be more clear in
this area.

Cheers


"Mike Treseler" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> SneakerNet wrote:
>
> > The receive module of the uart has these I/Os:
> > clock: input
> > baudclock: input
> > RxD: input
> > Data_FromPC[7..0]: output

>
>
>
> That would be Data_To_PC
>
>
>
>
> > RxComplete: output
> >
> > The I/O's are self-explanatory.
> > Now how can i use the RxComplete signal to implement the buffer? Help.

Any
> > info/advice appreciated.

>
>
>
>
> 1 8 8
> RxD]---[UART]---/--[FIFO]--/---[Data_To_PC
>
>
>
> -- Mike Treseler
>



 
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