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VHDL - Re: Repetitive code (Newbie)

 
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Old 08-07-2003, 04:48 AM   #1
Default Re: Repetitive code (Newbie)



"Ajeetha Kumari" <> a écrit dans le message de news:
...
> Hi,
> Look for GENERATE construct, I think that should fit your need.
>
> HTH,
> Ajeetha


I know GENERATE but can I use it with ATTRIBUTE ?
If yes, how uses it in the declaratory part of the ARCHITECTURE block ?

Thanks in advance

smu

> http://www.noveldv.com
> "smu" <> wrote in message

news:<3f2fd735$0$16171$>...
> > I try to find a elegant way to code a component in order to employ it

with
> > different value of a constant.
> >
> > The code is :
> >
> > library IEEE;
> > use IEEE.STD_LOGIC_1164.ALL;
> >
> > entity c_nibble is
> > Port ( input : in std_logic_vector(3 downto 0);
> > output : out std_logic_vector(3 downto 0));
> > end c_nibble;
> >





smu
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