writing cordic

Hi,

I'm writing a little and simplified version of the cordic algorithm.
But I can't understand why the following code doesn't work. I'm using
Modelsim, and during the simulation the signals X, Y, Z never are
always undefined, nor I get any other result.
I post the code. Thanks a lot for any help,
Gnome


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity vectors is
generic(
WIDTH : integer := 16;
PIPELINE : integer := 20);
port (
clk : in std_logic;

Xi, Yi : in signed(WIDTH -1 downto 0) := conv_signed('1', WIDTH);
Xj, Yj : out signed(WIDTH -1 downto 0);
Zi : inout signed(WIDTH -1 downto 0) := conv_signed('1', WIDTH)
);
end vectors;

architecture dataflow of vectors is

-- signals
type XYvector is array(PIPELINE downto 0) of signed(WIDTH -1 downto 0);
type Zvector is array (PIPELINE downto 0) of signed(19 downto 0);


-- returns atan(1/2^n)
function FATAN(n :natural) return integer is
[...]
end FATAN;


-- shift right of 1 bit
function shiftright(vect: signed) return signed is
variable tmp : signed(vect'range);
begin
-- tmp(vect'high) := vect(vect'high); ?????
tmp(vect'high) := '0';
for i in vect'high - 1 downto 0 loop
tmp(i) := vect(i);
end loop; -- i'0' + vect(vect'high downto 1);
return tmp;
end shiftright;


signal X, Y : XYvector;
signal Z, atan : Zvector;

begin

-- init
X(0) <= Xi;
Y(0) <= Yi;


Z(0)(19 downto 4) <= Zi;
Z(0)(3 downto 0) <= (others => '0');


p2: process(clk)
begin
for n in 0 to PIPELINE -1 loop
if(clk'event and clk='1') then
atan(n) <= conv_signed(fatan(n), 20);
if Z(n) >= 0 then
X(n+1) <= X(n) - shiftright(Y(n));
Y(n+1) <= Y(n) + shiftright(X(n));
Z(n+1) <= Z(n) - fatan(n);
else
X(n+1) <= X(n) + shiftright(Y(n));
Y(n+1) <= Y(n) - shiftright(X(n));
Z(n+1) <= Z(n) + atan(n);
end if;
end if;
end loop;
end process;

-- output

Xj <= X(PIPELINE);
Yj <= Y(PIPELINE);

end dataflow;

Gnome