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Re: Is this OK?

 
 
Mario Trams
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      07-22-2003
Matt Gessner wrote:

> Hi, all,
>
> I have a question about whether the following is a) synchronous (I believe
> it is) and b) advisable:
>
> signal counter: std_logic_vector (4 downto 0);
> signal clk: std_logic;
> signal cclk: std_logic;
>
> processa: process (clk) is
> begin
> if rising_edge (clk) then
> counter <= counter + 1;
> end if;
> end process;
>
> cclk <= counter (4);
>
> processb: process (cclk) is
> begin
> if rising_edge (cclk) then
> null; -- do something interesting
> end if;
> end process;
>
> Part of me screams "No, don't do it!" because I'm making a clock
> out of something that's not //really// a clock. Is this is a problem?
>
> Essentially, I'm scaling clk down by 8. In general, is this the
> way to do this? Is there something more advisable?


Hi Matt,

when you speak for VHDL, this is definitively not a problem an
is working perfectly.

When you speak for synthesis (FPGAs, CPLDs, etc.), this might be a
problem.
First of all, you should "inform" your synthesis tool that cclk
is a clock so that it uses appropriate routing ressources for that
signal (clock distribution network).
But the more complicated issue is that there is a small phase-shift
between the D-FlipFlops clocked by clk and the ones clocked by cclk.
In fact, cclk comes a little later than clk. In the case when
ordinary signals are exchanged between the two clocking domain your
design might not work. This is especially true for the signals
generated inside the clk domain.

I'm usually go the following way:

processa: process (clk)
begin
if rising_edge (clk) then
counter <= counter + 1;
cclk_dly1 <= cclk;
end if;
end process;

cclk <= counter (4);

processb: process (clk)
begin
if rising_edge (clk) then
if cclk='1' and cclk_dly1='0' then
null; -- do something interesting
end if;
end if;
end process;

That is, everything is clocked by one and the same clock now.
cclk and cclk_dly1 are used as enable for the second part. I.e.
the "interesting stuff" is done only one cycle after cclk turned
high.

NOTE: The stuff above is not a 1:1 replacement for your code due
to the 1-cycle delay!

I hope this helps,
Mario


 
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