Velocity Reviews > VHDL > Slow Synthesis

Slow Synthesis

Jeremy Pyle
Guest
Posts: n/a

 07-22-2003
Here is my code that divides a 32-bit number by a 32-bit number, where both
operands are of type UNSIGNED(31 downto 0) and provides a 16-bit fractional
number(the divisor is always greater than the dividend).

process(CLK)
variable count : integer range -1 to 15 := -1;
variable tempVal : UNSIGNED(47 downto 0);
begin
if(RISING_EDGE(CLK) and go = '1') then
if(count = -1) then
tempVal(47 downto 32) := (others => '0');
tempVal(31 downto 0) := dividend;
quotient <= (others => '0');
count := 15;
end if;

tempVal := SHL(tempVal, CONV_UNSIGNED(1,1));

if(tempVal >= divisor) then
quotient(count) <= '1';
tempVal := tempVal - divisor;
end if;
count := count - 1;
end if;
end process;

When I synthesize this, my maximum clock frequency is 53.110Mhz. Is there a
reason why this code runs so slowly? Am I doing something that I shoudln't
be doing? Now, I haven't tested this code yet, so if functionally it's
wrong, just ignore that, but why is it so slow? Thanks for any help.

Ralf Hildebrandt
Guest
Posts: n/a

 07-22-2003
Hi Jeremy!

> process(CLK)
> variable count : integer range -1 to 15 := -1;
> variable tempVal : UNSIGNED(47 downto 0);
> begin
> if(RISING_EDGE(CLK) and go = '1') then
> if(count = -1) then
> tempVal(47 downto 32) := (others => '0');
> tempVal(31 downto 0) := dividend;
> quotient <= (others => '0');
> count := 15;
> end if;
>
> tempVal := SHL(tempVal, CONV_UNSIGNED(1,1));
>
> if(tempVal >= divisor) then

This will be synthesized as a (subtractor) adder. If you set higher
clock-constraints or force the synthesis tool to use
more speed - if ths adder is in the critical path.

> quotient(count) <= '1';
> tempVal := tempVal - divisor;

> end if;
> count := count - 1;

....and the 3rd one.
Note: I only want to give you the hint, that there are 3 adders inside

> end if;
> end process;

> When I synthesize this, my maximum clock frequency is 53.110Mhz. Is there a
> reason why this code runs so slowly?

Well.. depending on your target process, this is not really slow.
Try to find the critical path. Try to speed it up.

Ralf

Andrew Paule
Guest
Posts: n/a

 07-23-2003
Hi Jeremy -

what architecture are you using for this design? Xilinx, Altera, Actel,
Quicklogic, other? Compiler? What is your design goal?

Andrew

Jeremy Pyle wrote:

>Here is my code that divides a 32-bit number by a 32-bit number, where both
>operands are of type UNSIGNED(31 downto 0) and provides a 16-bit fractional
>number(the divisor is always greater than the dividend).
>
> process(CLK)
> variable count : integer range -1 to 15 := -1;
> variable tempVal : UNSIGNED(47 downto 0);
> begin
> if(RISING_EDGE(CLK) and go = '1') then
> if(count = -1) then
> tempVal(47 downto 32) := (others => '0');
> tempVal(31 downto 0) := dividend;
> quotient <= (others => '0');
> count := 15;
> end if;
>
> tempVal := SHL(tempVal, CONV_UNSIGNED(1,1));
>
> if(tempVal >= divisor) then
> quotient(count) <= '1';
> tempVal := tempVal - divisor;
> end if;
> count := count - 1;
> end if;
> end process;
>
>
>When I synthesize this, my maximum clock frequency is 53.110Mhz. Is there a
>reason why this code runs so slowly? Am I doing something that I shoudln't
>be doing? Now, I haven't tested this code yet, so if functionally it's
>wrong, just ignore that, but why is it so slow? Thanks for any help.
>
>
>
>

Jerold Green
Guest
Posts: n/a

 07-23-2003
Remember that a variable is assigned its value immediately. Its new value
is available for subsequent assignments and tests in the same clock cycle.
The speed relates to the amount of combinatorial logic between clock edges.
If you look at tempVal, you have many levels of logic:
1) mux between previous value and dividend
2) left shift (no logic, just routing)
3) comparison
4) conditional subtraction

comparison is a subtraction operation, which is a ripple operation over all
48 bits (the comparison and subtraction are the same operation). So there
is a LOT of logic to get the next value of tempVal.

Keep in mind that this is not software. Re-using the same variable for
multiple assignments is generally a bad idea.

Also take a look at the quotient assignment. Making it a shift register and
assigning to the low bit would speed that up. It's also at the end of the
combinatorial chain
if (...) then
quotient <= quotient(14 downto 0) & '1';
else
quotient <= quotient(14 downto 0) & '0';
end if;
(my version of SHL)
You didn't say what speed the part is.
Does it have to take 16 clocks? You could try pipelining it, at least doing
the initialization on a separate clock.

Try not to assign count twice in the same clock cycle.

"Jeremy Pyle" <(E-Mail Removed)> wrote in message
news:ig1Ta.166053\$(E-Mail Removed)...
> Here is my code that divides a 32-bit number by a 32-bit number, where

both
> operands are of type UNSIGNED(31 downto 0) and provides a 16-bit

fractional
> number(the divisor is always greater than the dividend).
>
> process(CLK)
> variable count : integer range -1 to 15 := -1;
> variable tempVal : UNSIGNED(47 downto 0);
> begin
> if(RISING_EDGE(CLK) and go = '1') then
> if(count = -1) then
> tempVal(47 downto 32) := (others => '0');
> tempVal(31 downto 0) := dividend;
> quotient <= (others => '0');
> count := 15;
> end if;
>
> tempVal := SHL(tempVal, CONV_UNSIGNED(1,1));
>
> if(tempVal >= divisor) then
> quotient(count) <= '1';
> tempVal := tempVal - divisor;
> end if;
> count := count - 1;
> end if;
> end process;
>
>
> When I synthesize this, my maximum clock frequency is 53.110Mhz. Is there

a
> reason why this code runs so slowly? Am I doing something that I

shoudln't
> be doing? Now, I haven't tested this code yet, so if functionally it's
> wrong, just ignore that, but why is it so slow? Thanks for any help.
>
>

Jeremy Pyle
Guest
Posts: n/a

 07-23-2003
Yeah, I am using Xilinx ISE. Where can I find out about the critical path?

Thanks,

Jeremy

"Dan RADUT" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) om...
> "Jeremy Pyle" <(E-Mail Removed)> wrote in message

news:<ig1Ta.166053\$(E-Mail Removed)>. ..
> > When I synthesize this, my maximum clock frequency is 53.110Mhz. Is

there a
> > reason why this code runs so slowly? Am I doing something that I

shoudln't
> > be doing? Now, I haven't tested this code yet, so if functionally it's
> > wrong, just ignore that, but why is it so slow? Thanks for any help.

>
> What tools are you using? What is the frequency you would like your design

to
> work at?
> To find out why the maximum clock frequency is limited to a certain value

look
> into the report files and see what is mentioned about the critical path

and
> the number of logic levels. Usually the maximum frequency is limited by

the
> number of logic levels and the corresponding net delays related to the

nets
> interconnecting these logic levels. The critical path lists all these

delays.
> To increase the maximum frequency you need to use certain options
> provided by the tool, such as retiming, in order to reduce the number of

logic
> levels in between registers.
>
> Are you using Xilinx ISE? I could tell you more if the answer is positive.
>
> Regards,
>
> Dan R

Jeremy Pyle
Guest
Posts: n/a

 07-23-2003
Sorry, I should have specified, I'm using a XiLinx chip, the XCV300. The
compiler I'm using is XiLinx ISE from the Webpack.

Jeremy

"Andrew Paule" <(E-Mail Removed)> wrote in message
news:NZlTa.83\$(E-Mail Removed)...
> Hi Jeremy -
>
> what architecture are you using for this design? Xilinx, Altera, Actel,
> Quicklogic, other? Compiler? What is your design goal?
>
> Andrew
>
> Jeremy Pyle wrote:
>
> >Here is my code that divides a 32-bit number by a 32-bit number, where

both
> >operands are of type UNSIGNED(31 downto 0) and provides a 16-bit

fractional
> >number(the divisor is always greater than the dividend).
> >
> > process(CLK)
> > variable count : integer range -1 to 15 := -1;
> > variable tempVal : UNSIGNED(47 downto 0);
> > begin
> > if(RISING_EDGE(CLK) and go = '1') then
> > if(count = -1) then
> > tempVal(47 downto 32) := (others => '0');
> > tempVal(31 downto 0) := dividend;
> > quotient <= (others => '0');
> > count := 15;
> > end if;
> >
> > tempVal := SHL(tempVal, CONV_UNSIGNED(1,1));
> >
> > if(tempVal >= divisor) then
> > quotient(count) <= '1';
> > tempVal := tempVal - divisor;
> > end if;
> > count := count - 1;
> > end if;
> > end process;
> >
> >
> >When I synthesize this, my maximum clock frequency is 53.110Mhz. Is

there a
> >reason why this code runs so slowly? Am I doing something that I

shoudln't
> >be doing? Now, I haven't tested this code yet, so if functionally it's
> >wrong, just ignore that, but why is it so slow? Thanks for any help.
> >
> >
> >
> >

>