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Conditional signal declaration

 
 
Willem Oosthuizen
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      07-16-2003
Is it possible to make signal declarations in an architecture conditional?

E.g.. Suppose I want to write some code for a combinatorial correlater. The
correlation length is specified as a generic.
Obviously the number of internal signals needed is dependant on the length.
One way is to define all signals needed for lengths up to a certain value.
This is a brute-force way of doing things. There must be anoher way.





 
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Charles M. Elias
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      07-16-2003
"Willem Oosthuizen" <(E-Mail Removed)> wrote in message news:<bf38lm$jtd$(E-Mail Removed)>...
> Is it possible to make signal declarations in an architecture conditional?
>
> E.g.. Suppose I want to write some code for a combinatorial correlater. The
> correlation length is specified as a generic.
> Obviously the number of internal signals needed is dependant on the length.
> One way is to define all signals needed for lengths up to a certain value.
> This is a brute-force way of doing things. There must be anoher way.


How about using a generic statement?

Charles
 
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ben cohen
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      07-16-2003
"Willem Oosthuizen" <(E-Mail Removed)> wrote in message news:<bf38lm$jtd$(E-Mail Removed)>...
> Is it possible to make signal declarations in an architecture conditional?
>
> E.g.. Suppose I want to write some code for a combinatorial correlater. The
> correlation length is specified as a generic.
> Obviously the number of internal signals needed is dependant on the length.
> One way is to define all signals needed for lengths up to a certain value.
> This is a brute-force way of doing things. There must be anoher way.


There is no way in VHDL to make signal declarations conditional.
The only other choice is to declare signals inside generate
statements, and use the "if condition(generics)" generate scheme to
generate the desired logic.
From LRM 93:
generate_statement ::=
generate_label :
generation_scheme generate
[ { block_declarative_item } -- <- signal declrations
begin ]
{ concurrent_statement }
end generate [ generate_label ] ;

block_declarative_item ::=
subprogram_declaration
| subprogram_body
| type_declaration
| subtype_declaration
| constant_declaration
| signal_declaration
| shared_variable_declaration
| file_declaration
| alias_declaration
| component_declaration
| attribute_declaration
| attribute_specification
| configuration_specification
| disconnection_specification
| use_clause
| group_template_declaration
| group_declaration

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* Component Design by Example ", 2001 isbn 0-9705394-0-1
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0-7923-8474-1
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Charles M. Elias
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      07-16-2003
(E-Mail Removed) (Charles M. Elias) wrote in message news:<(E-Mail Removed). com>...
> "Willem Oosthuizen" <(E-Mail Removed)> wrote in message news:<bf38lm$jtd$(E-Mail Removed)>...
> > Is it possible to make signal declarations in an architecture conditional?
> >
> > E.g.. Suppose I want to write some code for a combinatorial correlater. The
> > correlation length is specified as a generic.
> > Obviously the number of internal signals needed is dependant on the length.
> > One way is to define all signals needed for lengths up to a certain value.
> > This is a brute-force way of doing things. There must be anoher way.

>
> How about using a generic statement?
>
> Charles


Sorry! I meant a generate statement.
 
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Ralf Hildebrandt
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      07-16-2003
Hi Willem!



> E.g.. Suppose I want to write some code for a combinatorial correlater. The
> correlation length is specified as a generic.
> Obviously the number of internal signals needed is dependant on the length.
> One way is to define all signals needed for lengths up to a certain value.
> This is a brute-force way of doing things. There must be anoher way.


If your synthesis tool does not comply, you could build a array whitch
elements are your signals.

Example:

subtype some_sulv_type is std_ulogic_vector(generic1 downto 0);
type some_sulv_arry_type is array(generic2 downto 0) of some_sulv_type;

signal all_signals : some_sulv_arry_type;


The size of the array depends on your generic parameter. It contains as
many elements as you need.


Ralf

 
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Mario Trams
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      07-17-2003
Willem Oosthuizen wrote:

> Is it possible to make signal declarations in an architecture conditional?
>
> E.g.. Suppose I want to write some code for a combinatorial correlater.
> The correlation length is specified as a generic.
> Obviously the number of internal signals needed is dependant on the
> length. One way is to define all signals needed for lengths up to a
> certain value. This is a brute-force way of doing things. There must be
> anoher way.


What is working fine for such conditional stuff is to use a C preprocessor.
That is, you have to put things like

#ifdef ...
....
#endif

etc. into your VHDL-code, pipe it through a C-preprocessor and give
the right options, and the result is a pure VHDL-file suitable for
compilation/synthesis.

Regards,
Mario

 
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