Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > how can I use a signal defined in one Architecture to another Architecture

Reply
Thread Tools

how can I use a signal defined in one Architecture to another Architecture

 
 
Muhammad Khan
Guest
Posts: n/a
 
      07-09-2003
Hello everybody,

I want to use the signal defined in one architecture in VHDL to
another architecture. I have two architecture in the same .vhd file
and I am using Component mapping. I required the result of calculation
of a signal to be used in second architecture. Can any one tell how to
defined signal so that it is globally visible to other architectures.

Regards

Khan
 
Reply With Quote
 
 
 
 
Mario Trams
Guest
Posts: n/a
 
      07-09-2003
Muhammad Khan wrote:

> I want to use the signal defined in one architecture in VHDL to
> another architecture. I have two architecture in the same .vhd file
> and I am using Component mapping. I required the result of calculation
> of a signal to be used in second architecture. Can any one tell how to
> defined signal so that it is globally visible to other architectures.


Hello Muhammad,

this is a common question.

The clean way for handling this is to feed the signal through
the port maps.

Regards,
Mario

--
----------------------------------------------------------------------
Digital Force / Mario Trams http://www.velocityreviews.com/forums/(E-Mail Removed)-chemnitz.de
http://www.velocityreviews.com/forums/(E-Mail Removed)
Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
Dept. of Computer Science Tel.: (+49) 371 531 1660
Chair of Computer Architecture Fax.: (+49) 371 531 1818
----------------------------------------------------------------------
 
Reply With Quote
 
 
 
 
Jon
Guest
Posts: n/a
 
      07-09-2003
Hi Khan,
If you declare a signal in a package and you include the package
then the signal can be globally used by all architectures that
reference that package. This is for simulation only and will not
work for synthesis.

Jon


(E-Mail Removed) (Muhammad Khan) wrote in message news:<(E-Mail Removed). com>...
> Hello everybody,
>
> I want to use the signal defined in one architecture in VHDL to
> another architecture. I have two architecture in the same .vhd file
> and I am using Component mapping. I required the result of calculation
> of a signal to be used in second architecture. Can any one tell how to
> defined signal so that it is globally visible to other architectures.
>
> Regards
>
> Khan

 
Reply With Quote
 
Ken McElvain
Guest
Posts: n/a
 
      07-10-2003


Jon wrote:

> Hi Khan,
> If you declare a signal in a package and you include the package
> then the signal can be globally used by all architectures that
> reference that package. This is for simulation only and will not
> work for synthesis.



This will work for synthesis in Synplify Pro 7.3.


>
> Jon
>
>
> (E-Mail Removed) (Muhammad Khan) wrote in message news:<(E-Mail Removed). com>...
>
>>Hello everybody,
>>
>>I want to use the signal defined in one architecture in VHDL to
>>another architecture. I have two architecture in the same .vhd file
>>and I am using Component mapping. I required the result of calculation
>>of a signal to be used in second architecture. Can any one tell how to
>>defined signal so that it is globally visible to other architectures.
>>
>>Regards
>>
>>Khan
>>


 
Reply With Quote
 
Mike Treseler
Guest
Posts: n/a
 
      07-10-2003
Ken McElvain wrote:

> Jon wrote:


>> If you declare a signal in a package and you include the package
>> then the signal can be globally used by all architectures that
>> reference that package. This is for simulation only and will not
>> work for synthesis.

>
> This will work for synthesis in Synplify Pro 7.3.


Cool. Never seen that in synthesis before.
How did you get test cases?

-- Mike Treseler

 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Can one declare more than one signal on one line? Merciadri Luca VHDL 4 11-01-2010 02:00 PM
Aside from delta cycles and/or resolution functions, how can the effective value of a signal differ from a driving signal of its? Colin Paul Gloster VHDL 0 01-11-2007 01:31 PM
#if (defined(__STDC__) && !defined(NO_PROTOTYPE)) || defined(__cplusplus) Oodini C Programming 1 09-27-2005 07:58 PM
ON Linux Platform: How can we build binaries for another architecture from 0x86 architecture rashmi C Programming 2 07-05-2005 02:31 PM
how to use static function defined in one file in another file is that impposiible in 'c ' rashmi C Programming 5 04-29-2005 03:26 PM



Advertisments