Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Array of std_logic_vector

Reply
Thread Tools

Array of std_logic_vector

 
 
Willem Oosthuizen
Guest
Posts: n/a
 
      07-09-2003
I have the following:

type AA is array(6 downto 0) of std_logic_vector(5 downto 0);
signal Thing: AA;

begin

Thing(0,0) <= '1';

......
The Synth complains about the assignment: "Indexing operation does not match
dimensionality of array"

Any suggestions?


 
Reply With Quote
 
 
 
 
Mario Trams
Guest
Posts: n/a
 
      07-09-2003
Willem Oosthuizen wrote:

> I have the following:
>
> type AA is array(6 downto 0) of std_logic_vector(5 downto 0);
> signal Thing: AA;
>
> begin
>
> Thing(0,0) <= '1';
>
> .....
> The Synth complains about the assignment: "Indexing operation does not
> match dimensionality of array"
>
> Any suggestions?


Of course, wrong indexing syntax.
It has to be

Thing(0)(0) <= '1';

(like indexing in C)

Regards,
Mario
 
Reply With Quote
 
 
 
 
Tim Hubberstey
Guest
Posts: n/a
 
      07-09-2003
Mario Trams wrote:
>
> Willem Oosthuizen wrote:
>
> > I have the following:
> >
> > type AA is array(6 downto 0) of std_logic_vector(5 downto 0);
> > signal Thing: AA;
> >
> > begin
> >
> > Thing(0,0) <= '1';
> >
> > .....
> > The Synth complains about the assignment: "Indexing operation does not
> > match dimensionality of array"
> >
> > Any suggestions?

>
> Of course, wrong indexing syntax.
> It has to be
>
> Thing(0)(0) <= '1';
>
> (like indexing in C)


More completely, it's not incorrect syntax but rather the wrong syntax
for this type of array. The thing(a,b) format is for multidimensional
arrays whereas thing(a)(b) is for an array of arrays, which is what you
have. For some reason, synthesizer makers have chosen to support arrays
of arrays but not multidimensional arrays. Multidimensional arrays are
perfectly legal for simulation.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
 
Reply With Quote
 
mathukutty mathukutty is offline
Junior Member
Join Date: Feb 2010
Posts: 1
 
      02-26-2010
Quote:
For some reason, synthesizer makers have chosen to support arrays
of arrays but not multidimensional arrays. Multidimensional arrays are
perfectly legal for simulation.
I tested both multidimensional arrays and array of arrays. Both are synthesizeable. I am using an Altera D2 Board with Quartus II simulator
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
inout std_logic_vector to array of std_logic_vector of generic length conversion... Thomas Rouam VHDL 6 11-09-2007 11:49 AM
ARRAY(n DOWNTO 0) OF STD_LOGIC_VECTOR(m DOWNTO 0) - VHDL freitass Hardware 0 11-01-2007 03:44 PM
generate and std_logic_vector array issue vince00001 VHDL 3 06-06-2007 03:28 AM
std_logic_vector Array Input Brad Smallridge VHDL 5 02-26-2007 05:47 PM
Array of generic width std_logic_vector in entity? Brandon VHDL 2 07-18-2005 01:25 PM



Advertisments