On Wed, 2 Jul 2003 07:30:46 +0200, "John T." <> wrote:
>What does it mean when I declare values in the entity, for example:
>
>ENTITY test IS
>PORT(
> dummy_1: IN std_logic := '1';
> dummy_2: IN std_logic := '0';
>
> dummy_3: OUT std_logic := '1';
> dummy_4: OUT std_logic := '1';
> dummy_5: OUT std_logic := '0'
>
>);
>END ENTITY test;
>
>Is this some sort of starting values? Are they only used in simulation
>or......?
1. For the input ports, this is the value that the signal will take
if the port is left open (either by being mapped to 'open' in the port
map, or by being left out of the port map altogether).
This works perfectly well in both simulation and synthesis, as long as
you aren't using tools supplied by Synopsys (in which case the default
value will be 0 regardless of the value you specified).
2. For the output ports, this is the value that the drivers will have
at elaboration time. If there are no drivers within the architecture
(i.e. you haven't made an assignment to the port of the form
dummy_1 <= something; ) this is the value of (the driver of) the
output port forever. Otherwise it is the value the port has until the
first signal assignment to the port runs, typically 1 delta cycle into
the simulation.
I don't usually see default values used for output ports in
synthesisable code. It can be useful to eliminate glitches in
simulation though, e.g. if the architecture is driving (say) '1', and
there's no initial value on the port, the output will be 'U' for 1
delta cycle before changing to '1'. With the initial value, it will
simply be '1'.
Another way of stating that is:
If you don't provide a value, the language provides an implicit
initialiser of 'U', e.g.
dummy_3: OUT std_logic := 'U';
Regards,
Allan.
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