Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Synthesis of STD_LOGIC

Reply
Thread Tools

Synthesis of STD_LOGIC

 
 
Christopher Bunk
Guest
Posts: n/a
 
      07-01-2003
Hey, I got a question about synthesizing STD_LOGIC. When it's synthesized is
it identical to a "bit". For simulation I realize that it was given other
values such as U, -, L and H, but which of these values work for simulation?
If I write a 'U' to it for example, and then I compare it to 'U' does that
work in simulation. Or what values will that work for in simulation?


Thanks.


 
Reply With Quote
 
 
 
 
Mike Treseler
Guest
Posts: n/a
 
      07-03-2003


Christopher Bunk wrote:
> Hey, I got a question about synthesizing STD_LOGIC. When it's synthesized is
> it identical to a "bit". For simulation I realize that it was given other
> values such as U, -, L and H, but which of these values work for simulation?


All of them.

> If I write a 'U' to it for example, and then I compare it to 'U' does that
> work in simulation.


yes.

-- Mike Treseler

 
Reply With Quote
 
 
 
 
Tim Hubberstey
Guest
Posts: n/a
 
      07-04-2003
Christopher Bunk wrote:
>
> Oh crap. Sorry I typed that wrong. I meant what values work for synthesis.
> I'm guessing that you can only compare to '1' and '0' for synthesis. Am I
> right?


Yes. There is no hardware analog of '-', 'U', 'X' or 'W' and while it
might be possible to construct something to implement comparisons
against 'Z', 'H', and 'L', I doubt that any synthesizer does it.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
boolean to std_logic valentin tihomirov VHDL 3 01-05-2004 04:48 PM
Re: boolean to std_logic David R Brooks VHDL 0 12-31-2003 11:13 PM
SOS! newbie question about synthesizable VHDL : synthesis run successfully but post-synthesis failed... walala VHDL 4 09-09-2003 08:41 AM
what are the possible reasons that successful pre-synthesis simulation + successful synthesis = failed post-synthes walala VHDL 4 09-08-2003 01:51 PM
SystemC std_logic resolved type zoro VHDL 2 07-05-2003 07:16 PM



Advertisments