The FIR uses many FPGA resource.How to reduce the resource.The coefficients

are from matlab.

Would any one give me advice on it or give me the fir example as the

reference.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.std_logic_arith.all;

use ieee.std_logic_signed.all;

entity fir is

(

clk:in std_logic;

x:in std_logic_vector(15 downto 0);

q

ut std_logic_vector(31 downto 0)

);

end fir;

architecture afir of fir is

signal x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15 ,x16,x17,x18:

std_logic_vector(15 downto 0);

signal s1,s2,s3,s4,s5,s6,s7,s8,s9:std_logic_vector(15 downto 0);

signal y1,y2,y3,y4,y5,y6,y7,y8,y9:std_logic_vector(31 downto 0);

constant h1:std_logic_vector:="0000000010001000"; --136

constant h2:std_logic_vector:="1111111010011010"; -- -358

constant h3:std_logic_vector:="0000000101110101"; --373

constant h4:std_logic_vector:="0000000010101110"; --174

constant h5:std_logic_vector:="1111110110000000"; -- -1280

constant h6:std_logic_vector:="0000100011001000"; --2248

constant h7:std_logic_vector:="1111100100111000"; -- -1736

constant h8:std_logic_vector:="1111011101111101"; -- -2179

constant h9:std_logic_vector:="0100101001001011"; --19019

begin

process(clk)

begin

if(clk'event and clk='1')then

x18<=x17;

x17<=x16;

x16<=x15;

x15<=x14;

x14<=x13;

x13<=x12;

x12<=x11;

x11<=x10;

x10<=x9;

x9<=x8;

x8<=x7;

x7<=x6;

x6<=x5;

x5<=x4;

x4<=x3;

x3<=x2;

x2<=x1;

x1<=x;

end if;

end process;

process(clk)

begin

if(clk'event and clk='1') then

s1<=signed(x1)+signed(x1

;

s2<=signed(x2)+signed(x17);

s3<=signed(x3)+signed(x16);

s4<=signed(x4)+signed(x15);

s5<=signed(x5)+signed(x14);

s6<=signed(x6)+signed(x13);

s7<=signed(x7)+signed(x12);

s8<=signed(x

+signed(x11);

s9<=signed(x9)+signed(x10);

end if;

end process;

process(clk)

begin

if(clk'event and clk='1') then

y1<=s

igned(s1)*signed(h1);

y2<=signed(s2)*signed(h2);

y3<=signed(s3)*signed(h3);

y4<=signed(s4)*signed(h4);

y5<=signed(s5)*signed(h5);

y6<=signed(s6)*signed(h6);

y7<=signed(s7)*signed(h7);

y8<=signed(s

*signed(h

;

y9<=signed(s9)*signed(h9);

end if;

end process;

process(clk)

begin

if(clk'event and clk='1') then

q<=signed(y1)+signed(y2)+signed(y3)+signed(y4)+sig ned(y5)

+signed(y6)+signed(y7)+signed(y

+signed(y9);

end if;

end process;

end afir;

--

Best Regards