Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > UART Implementation

Reply
Thread Tools

UART Implementation

 
 
Anand P Paralkar
Guest
Posts: n/a
 
      06-26-2003
Hi,

I need to implement a simple UART. By simple, I mean the UART only needs
a transmitter which would take parallel data and shift it out serially at
a fixed baud rate. The receiver receives serial input data at the same,
fixed baud rate, which must be output in parallel, one byte at a time.
In short, the UART should look something like:

+---------------+
--->| |
Parallel Data In | |-----> Tx to RS232 line driver
--->| |
| |
<---| |
Parallel Data Out | |<----- Rx from RS232 line driver
<---| |
| |
| |
+---------------+

The UART should perform:

1. Start bit detection/generation.
2. Stop bit detection/generation.
3. Data bits sampling/transmitting.

The UART does NOT need to have:

1. Programmable baud rate.
2. Programmable character length (6, 7 or 8 bits per character).
3. Programmable stop bit length (1, 1.5 or 2 bits per character).
4. Parity checking.
5. RTS/CTS based or any other type of flow control.
6. Buffering (using Rx and Tx FIFOs).
7. Interrupt generation.

Could you please suggest a design for the receiver section. (I have seen a
few articles on the Internet, but most of them are "datasheets" of UARTs.
None of them discuss the internal design.)

I would be particularly interested in knowing how to determine the
required clock frequency for a given baud rate in the receiver section.

Why do people choose 3X or 16X clocks (times baud rate) in typical UART
implementations?

Thank you for your time.

Thanks,
Anand

 
Reply With Quote
 
 
 
 
Mario Trams
Guest
Posts: n/a
 
      06-27-2003
Anand P Paralkar wrote:

<snip>

> Could you please suggest a design for the receiver section. (I have seen a
> few articles on the Internet, but most of them are "datasheets" of UARTs.
> None of them discuss the internal design.)


Did you ever heard about this magic tool called "google"
Searching for vhdl+uart returns tons of links.

> I would be particularly interested in knowing how to determine the
> required clock frequency for a given baud rate in the receiver section.
>
> Why do people choose 3X or 16X clocks (times baud rate) in typical UART
> implementations?


This is because you somehow have to "hit" the middle of the bit frames
and syncronize the receiver with the incoming stream. That is, you wait
for the start bit (sampled by the oversampling clock), then you wait
half the time and sample the stop bit (i.e. you sample it at the 8th
oversampling clock assuming a 16x clock). Then you wait another 16
cycles and sample the first data bit etc.

Assuming absolutely precise (constant) aligned sender and receiver
clocks, you would not need this oversampling at all.
If you know the worst case clock difference between the sender and
the receiver and the bit length of a transmitted word, then you can
calculate how much oversampling is required in order the guarantee
a flawless operation. Of course, when the clocks are totally out of
sync the oversampling won't help.

Regards,
Mario

 
Reply With Quote
 
 
 
 
Rudolf Usselmann
Guest
Posts: n/a
 
      07-07-2003
Anand P Paralkar <(E-Mail Removed)> wrote in message news:<(E-Mail Removed)>...
> Hi,
>
> I need to implement a simple UART. By simple, I mean the UART only needs
> a transmitter which would take parallel data and shift it out serially at
> a fixed baud rate. The receiver receives serial input data at the same,
> fixed baud rate, which must be output in parallel, one byte at a time.
> In short, the UART should look something like:
>
> +---------------+
> --->| |
> Parallel Data In | |-----> Tx to RS232 line driver
> --->| |
> | |
> <---| |
> Parallel Data Out | |<----- Rx from RS232 line driver
> <---| |
> | |
> | |
> +---------------+
>
> The UART should perform:
>
> 1. Start bit detection/generation.
> 2. Stop bit detection/generation.
> 3. Data bits sampling/transmitting.
>
> The UART does NOT need to have:
>
> 1. Programmable baud rate.
> 2. Programmable character length (6, 7 or 8 bits per character).
> 3. Programmable stop bit length (1, 1.5 or 2 bits per character).
> 4. Parity checking.
> 5. RTS/CTS based or any other type of flow control.
> 6. Buffering (using Rx and Tx FIFOs).
> 7. Interrupt generation.
>
> Could you please suggest a design for the receiver section. (I have seen a
> few articles on the Internet, but most of them are "datasheets" of UARTs.
> None of them discuss the internal design.)
>
> I would be particularly interested in knowing how to determine the
> required clock frequency for a given baud rate in the receiver section.
>
> Why do people choose 3X or 16X clocks (times baud rate) in typical UART
> implementations?
>
> Thank you for your time.
>
> Thanks,
> Anand



Check out our web site, we provide a free IP core of
a simple UART.

Regards,
rudi
--------------------------------------------------------
www.asics.ws --- Solutions for your ASIC/FPGA needs ---
----------------- FPGAs * Full Custom ICs * IP Cores ---
FREE IP Cores --> http://www.asics.ws/ <-- FREE IP Cores
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Uart and clock Neil VHDL 1 06-25-2005 03:33 PM
UART receiver Konstantin Dols VHDL 0 12-12-2004 12:24 PM
Issues on clockless UART Shashi VHDL 3 04-22-2004 12:05 AM
Issues on Shift Register in a Clockless UART Shashi VHDL 0 04-20-2004 11:51 PM
Re: vhdl UART Mike Treseler VHDL 1 08-10-2003 08:45 PM



Advertisments