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Why is this not a locally static choice?

 
 
Charles M. Elias
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      06-26-2003
In the following code fragment Active-HDL flagged the "case oe_l is" line as an
error because oe_l is not locally static. Why is this so? "numbuffs" is
not going to change during execution.

Best regards,

Charles

------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
------------------------------------------------------------------------
entity BiDir is
generic( bufflength : natural := 8;
numbuffs : natural := 4 );
port ( oe_l : in std_logic_vector( 0 to numbuffs - 1 );
a : inout std_logic_vector( bufflength - 1 downto 0 );
b0 : inout std_logic_vector( bufflength - 1 downto 0 );
b1 : inout std_logic_vector( bufflength - 1 downto 0 );
b2 : inout std_logic_vector( bufflength - 1 downto 0 );
b3 : inout std_logic_vector( bufflength - 1 downto 0 );
dirab : in std_logic
);
end BiDir;
------------------------------------------------------------------------
architecture archBiDir of BiDir is

begin
pio : process( oe_l, dirab, a, b0, b1, b2, b3 )
begin
case oe_l is
when "0111" =>
if dirab = '1' then
a <= ( others => 'Z' );
b0 <= a;
else
...
 
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Egbert Molenkamp
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      06-26-2003
Since you have used a generic for numbuffs you can instantiate multiple
entities of BiDir with different values for the generic. Therefore it is not
'locally' static.

If you change the line:
oe_l : in std_logic_vector( 0 to numbuffs - 1 );
in
oe_l : in std_logic_vector( 0 to 3 );
it will work.

Notice also that the line:
case oe_l is
when "0111" =>
Would give an error if the generic numbuffs is not equal to 4.

Egbert Molenkamp

"Charles M. Elias" <(E-Mail Removed)> schreef in bericht
news:(E-Mail Removed) m...
> In the following code fragment Active-HDL flagged the "case oe_l is" line

as an
> error because oe_l is not locally static. Why is this so? "numbuffs" is
> not going to change during execution.
>
> Best regards,
>
> Charles
>
> ------------------------------------------------------------------------
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> ------------------------------------------------------------------------
> entity BiDir is
> generic( bufflength : natural := 8;
> numbuffs : natural := 4 );
> port ( oe_l : in std_logic_vector( 0 to numbuffs - 1 );
> a : inout std_logic_vector( bufflength - 1 downto 0 );
> b0 : inout std_logic_vector( bufflength - 1 downto 0 );
> b1 : inout std_logic_vector( bufflength - 1 downto 0 );
> b2 : inout std_logic_vector( bufflength - 1 downto 0 );
> b3 : inout std_logic_vector( bufflength - 1 downto 0 );
> dirab : in std_logic
> );
> end BiDir;
> ------------------------------------------------------------------------
> architecture archBiDir of BiDir is
>
> begin
> pio : process( oe_l, dirab, a, b0, b1, b2, b3 )
> begin
> case oe_l is
> when "0111" =>
> if dirab = '1' then
> a <= ( others => 'Z' );
> b0 <= a;
> else
> ...



 
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Charles M. Elias
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Posts: n/a
 
      06-26-2003
"Egbert Molenkamp" <(E-Mail Removed)> wrote in message news:<bder9n$pbt$(E-Mail Removed)>...
> Since you have used a generic for numbuffs you can instantiate multiple
> entities of BiDir with different values for the generic. Therefore it is not
> 'locally' static.
>
> If you change the line:
> oe_l : in std_logic_vector( 0 to numbuffs - 1 );
> in
> oe_l : in std_logic_vector( 0 to 3 );
> it will work.
>
> Notice also that the line:
> case oe_l is
> when "0111" =>
> Would give an error if the generic numbuffs is not equal to 4.
>
> Egbert Molenkamp
>
> "Charles M. Elias" <(E-Mail Removed)> schreef in bericht
> news:(E-Mail Removed) m...
> > In the following code fragment Active-HDL flagged the "case oe_l is" line

> as an
> > error because oe_l is not locally static. Why is this so? "numbuffs" is
> > not going to change during execution.
> >
> > Best regards,
> >
> > Charles
> >
> > ------------------------------------------------------------------------
> > library IEEE;
> > use IEEE.STD_LOGIC_1164.all;
> > ------------------------------------------------------------------------
> > entity BiDir is
> > generic( bufflength : natural := 8;
> > numbuffs : natural := 4 );
> > port ( oe_l : in std_logic_vector( 0 to numbuffs - 1 );
> > a : inout std_logic_vector( bufflength - 1 downto 0 );
> > b0 : inout std_logic_vector( bufflength - 1 downto 0 );
> > b1 : inout std_logic_vector( bufflength - 1 downto 0 );
> > b2 : inout std_logic_vector( bufflength - 1 downto 0 );
> > b3 : inout std_logic_vector( bufflength - 1 downto 0 );
> > dirab : in std_logic
> > );
> > end BiDir;
> > ------------------------------------------------------------------------
> > architecture archBiDir of BiDir is
> >
> > begin
> > pio : process( oe_l, dirab, a, b0, b1, b2, b3 )
> > begin
> > case oe_l is
> > when "0111" =>
> > if dirab = '1' then
> > a <= ( others => 'Z' );
> > b0 <= a;
> > else
> > ...


Egbert,

Thanks!

Charles
 
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