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[Fwd: Vhdl dynamic generation]

Mike Treseler
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-------- Original Message --------
Subject: Vhdl dynamic generation
Date: Wed, 25 Jun 2003 09:22:37 -0700 (PDT)
From: silicia mando


Besides "Generic" and "Global" variable concepts,
do you think that VHDL is suitable for "dynamic"

Let's take the following examples:

if implementing a conventional FIR filter with known
input range, then we can optimally pre-calculate the
minimum wordldength at each FIR node. These optimal
values should be preferably used when implementing
this filter.

However, can we set (from the same synthesiser
environment ) these wordlengths dynamically when
generating the VHDL code for this FIR for any input
range values ?.

Wondering if we can call a "function" that allows us
to undertake mathematical computation before setting
the wordlength at each node.

If not, i can think on generating a text file where
all the nodes wordlength are included. This file will
be used in setting the internal FIR wordlength?

But as i said, i am looking to work in the same
environement, without calling or running another

Things might seem harder if we want to generate a core
for flt2 cascaded to flt1, and i want to use solely
the same synthesiser without calling in other

i expect this is not possible since most of the core
generator has front end NOT using VHDL, especially
when considering that a function call will return a
value and not a parametrised vhdl code

if i am wrong, i will be glad to have hints from you.

In summary i am wondering on the following issue:

could we have such call


using the same synthesiser

how this code can be inserted DYNAMICALLY in other
vhdl code project?
is it better to develop a user library, so the user
can set these coefficients in the call instantiation ?

say i develop a filter with array input at the entity
this array contains the filter coefficient. so when
calling this filter i just send the appropriate

sorry if my question is so confusing

Thanks for your time

Kind Regards

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Mike Treseler
Posts: n/a
Silicia Mando wrote:

> Hello,
> Besides "Generic" and "Global" variable concepts,
> do you think that VHDL is suitable for "dynamic"
> parametrization?

The best you can do in VHDL for synthesis
is to prepackage a constant array and set an index on
the command line as a generic to pick up
the proper set of constants.

You could recalculate and even generate the
package code from a vhdl simulator using
the math library.

However are many other preprocessors and scripting
languages that could do the same thing without
tying up a license.

-- Mike Treseler

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abida abida is offline
Junior Member
Join Date: Apr 2011
Posts: 3
i need code for fixed width multiplier
plzzzzzzz help me
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