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I have a mismatch in Modelsim behavioral simulations using 1) VHDL
testbench in ISE and 2) manual entry of stimuli.

While the vector inputs are same in time and values in both cases, the
output, however, is different. The manual simulation seems working as
designed but the testbench based simulation has a delayed output and
the current state of FSM is stuck to certain state.

This is the first time I have encountered this problem, otherwise I
have been consistently getting same results whether I manually simulate
the design or use a testbench. I am quite clueless here. I don't know
whether the problem is attributed to the Modelsim or the design itself
since Modelsim gives two different results on same source file, the
mode of simulation is different though.

Regards,

YZ

hey Yaseen;
i dont think so. modelsim and ur testbench should produce same results.
modelsim is basically the simulation tool. check at the clock, input
values, control signals and since you have to force values in modelsim,
check out if u doing it correctly. the timing is the same.

Cheers
Abbs