Matt Clement a écrit :
> Hello
>
> I have built both a PIC microchip controlled clock divider as well as a CPLD
> clock divider in the past for various projects but was told today that a
> VHDL or discrete logic will always be "cleaner" than one run with a PIC. Is
> this accurate? We are looking to create a clock on the order of 10-20Khz
> from something faster. We are looking to get a very low jitter output.
> Anyone offer any data backing either design?
>
> thanks
Good evening,
I do not agree fully with the one "cleaner" than the other. "Differents"
would be better...
If you wants an asynchronous divider (driven by original clock), PIC
cannot handle it. PLD can, but jitter will no be handled very well.
If you wants a synchronous divider (synchronized to an external clock),
PIC has its output latched from its main clock. PLD can have a same
output configuration.
10..20 kHz can be handled by both them in the same manner if the main
clock is large enought to use an integer count value for compute wave
timings.
But ... you cannot use "C" to write the PLD description, so do not use
it for pic if you wants to have comparable results

Use asm.
Pascal