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Gentlemen,

I was wondering if it is possible to overcome the problem with
"generate" statement, which implies static range?

The problem occurs when it is necessary to generate an array of the size
which
is defined in some other data file. In other words the range for generate
statement
is not static. It is possible to pass these parameters as generic,
but then the problem is transferred to the upper level of hierarchy,
because component indentation
is a concurrent statement and reading parameters from the file is a
sequential process.

Perhaps someone can suggest the way to cope with this issue (apart from
generating vhdl code by some script

Thank you.

--
Alex

Alex wrote:

> It is possible to pass these parameters as generic,
> but then the problem is transferred to the upper level of
> hierarchy, because component indentation
> is a concurrent statement and reading parameters from the file is a
> sequential process.

Generics can also be passed on the
command line from a script.

-- Mike Treseler

Mike,

Hm. But is it possible to do it only by using VHDL constructs?

It seems to be pretty useful when, for example, one need to generate ROM
depending on the size of some external data, and the left of the BRAM
block
reserve as RAM.

So far I see the only alternative solution is to run simulation from Tcl
script
via vsim -gname=val (I guess that what you have mentioned).


On Sun, 16 Apr 2006 22:24:11 +0100, Mike Treseler
<> wrote:

> Alex wrote:
>
>> It is possible to pass these parameters as generic,
>> but then the problem is transferred to the upper level of
>> hierarchy, because component indentation
>> is a concurrent statement and reading parameters from the file is
>> a sequential process.
>
> Generics can also be passed on the
> command line from a script.
>
> -- Mike Treseler



--
Alex

Alex wrote:
> Mike,
>
> Hm. But is it possible to do it only by using VHDL constructs?

Sure.
Just package the constants as
a vhdl array or record instead of a file.

-- Mike Treseler

I saw this once in a simulation model for a pal that read in the jedec
file and used generate statements to create the and-tree from the
fusemap.

Initialize a constant with a function call, and then within that
function, use text-io to read/process the data file and compute the
value for the constant.

Then use the constant in a generate statement.

Note that the file gets read during the elaboration phase, not the
simulation phase. However, since most synthesis tools don't separate
the phases, they still cannot support text-io, even in "elaboration".
Too bad... could be a market differentiator here... Anyone at
synplicity listening?...

For synthesis, you're stuck with having a separate app/script process
the file to create the value for the generic, which you then pass in as
a command-line parameter to the simulation/synthesis tool.

Hope this helps,

Andy

Yes, but this will work in case when those constants are known a priori.
What can be done when the data in stored somewhere else and need to be
read only
when the design is compiled(& simulated)?
Essentially the question can be rephrased as is it possible to perform
some modification to
a shared variable before instantiating a component?


> Alex wrote:
>> Mike,
>> Hm. But is it possible to do it only by using VHDL constructs?
>
> Sure.
> Just package the constants as
> a vhdl array or record instead of a file.
>
> -- Mike Treseler



--
Alex

Andy,

Haven't seen your post before answering to Mike.

So how can I do this "elaboration" stage, i.e. where can I call a
function prior
the indentation?

> I saw this once in a simulation model for a pal that read in the jedec
> file and used generate statements to create the and-tree from the
> fusemap.
>
> Initialize a constant with a function call, and then within that
> function, use text-io to read/process the data file and compute the
> value for the constant.
>
> Then use the constant in a generate statement.
>
> Note that the file gets read during the elaboration phase, not the
> simulation phase. However, since most synthesis tools don't separate
> the phases, they still cannot support text-io, even in "elaboration".
> Too bad... could be a market differentiator here... Anyone at
> synplicity listening?...
>
> For synthesis, you're stuck with having a separate app/script process
> the file to create the value for the generic, which you then pass in as
> a command-line parameter to the simulation/synthesis tool.
>
> Hope this helps,
>
> Andy
>



--
Alex

Alex wrote:
> Yes, but this will work in case when those constants are known a priori.
> What can be done when the data in stored somewhere else and need to be
> read only when the design is compiled(& simulated)?

One way or another that file has to be converted
into vhdl objects on the fly.
Andy's textio function call idea is a clever way
to do this directly for simulation.

For synthesis I know of no way to handle a
text file directly.
If the process generating the file is automated,
you could have it build a vhdl package file or
command line generic as the data is generated.
I would prefer to write a separate program or script to do
the conversion, and add this dependency to my Makefile.
If you can tolerate vhdl textio, a simulation testbench could
also do the text file conversion before synthesis.

-- Mike Treseler

Alex,

The vhdl standard calls for two levels of processing the code before
executing it, a la ada.

Analysis stage is essentially compilation.
Elaboration stage handles any deferred constant definitions, generics,
generate statements, configurations (component/entity/archietecture
bindings), etc. This would be similar to linking the code in SW.

Execution is running the simulation.

Some simulators transparently merge elaboration and execution, others
don't (Cadence NCvhdl for one).

Synthesis never executes anything, and most (all?) combine analysis and
elaboration into one step. All synthesis tools understand some parts
of your code are executed, and only the results are synthesized, such
as logic and/or arithmetic on static operands, loop indices (unrolled),
etc. Unfortunately, none go so far as to allow something as inherently
unsynthesizable as text-io, even in static situations (i.e. the
resulting hardware would not read the file, instead the file is read
during synthesis, and the results are used to synthesize the hardware).

Example:

architecture sim of my_entity is
function init() return integer is
-- do text-io here
end function;

constant gen_val : integer := init(); -- call init while initializing
constant (in elab)

begin

for i in 0 to gen_val - 1 generate
....
end generate;
end architecture;

Note that the init function could return a record or array, if one file
is used to initialize multiple constants. You'd have to declare a
constant of the array or record type, initialize it with the function
call, then declare/initialize other constants with elements of the
constant array/record.

Hope this helps,

Andy


Alex wrote:
> Andy,
>
> Haven't seen your post before answering to Mike.
>
> So how can I do this "elaboration" stage, i.e. where can I call a
> function prior
> the indentation?
>
>
> --
> Alex

Andy wrote:

> The vhdl standard calls for two levels of processing the code before
> executing it, a la ada.

.... lucid lecture liquidated

> Some simulators transparently merge elaboration and execution, others
> don't (Cadence NCvhdl for one).

For modelsim,
vcom -c my_entity.vhd
"analyzes" the design and flags syntax errors.

vsim -c my_entity
"elaborates" the design and finds structural errors.

vsim test_my_entity -do "run -all"
elaborates the testbench using the pre-analyzed design
brings up the GUI and executes processes until all are waiting.

> Synthesis never executes anything, and most (all?) combine analysis and
> elaboration into one step.

Leonardo has separate elaborate and analyze
commands, but they require a level-3 license.
But as all the others, it punts file declarations.

-- Mike Treseler