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Search: Posts Made By: Thom
Forum: VHDL 04-11-2008
Replies: 0
Views: 1,242
Posted By Thom
Identifier "signed" is not directly visible

New to VHDL and need some newbee help...

Here is the begining of my code:


----------------------------------------------------
library ieee;
USE ieee.std_logic_1164.all;
USE...
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