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Search: Posts Made By: marina_yassa
Forum: VHDL 03-29-2013
Replies: 2
Views: 2,482
Posted By marina_yassa
entity SA is Port (...

entity SA is
Port ( s1,s2,s3,s4,t1,t2,t3,t4,i1,i2,i3,i4: in std_logic_vector (7 downto 0);
p1,p2,p3,p4 : out std_logic_vector (7 downto 0) );
end SA;

architecture Behavioral of...
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