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Forum: VHDL 07-28-2011
Replies: 6
Views: 2,416
Posted By RADNOR
figure out at least something by yourself about...

figure out at least something by yourself about your homework assignment before posting a lameass question like "how to do it"
Forum: VHDL 07-20-2011
Replies: 3
Views: 2,725
Posted By RADNOR
Ok here is my solution. It generates N amount of...

Ok here is my solution. It generates N amount of muxes, and each mux has N inputs. Each input and output is 16 bits, so total width of output from all muxes is N * 16 bits.
array: for index in N-1...
Forum: VHDL 07-20-2011
Replies: 3
Views: 2,725
Posted By RADNOR
well thanks for advice, but as you yourself...

well thanks for advice, but as you yourself noticed its not gona be that efficient because of its nested comparison nature.

well it actually turns out that i do not need to see if others are zero,...
Forum: VHDL 07-20-2011
Replies: 3
Views: 2,725
Posted By RADNOR
MUX with generate statement

Hello,

lets say i have some signal select_signal, and that is one-hot type of a signal, so at any time only one of its bits is 1, others are 0.

The number of bits in that signal depends on the...
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