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Forum: VHDL 02-08-2007
Replies: 2
Views: 535
Posted By DualCore
counters in fsm

i am trying to increment value of 4-bit counter in fsm , but instead of bin 01 its adding 02 and although the state advancement if on every risiing edge of clk , this counter is incrementing on...
Forum: VHDL 10-17-2006
Replies: 4
Views: 435
Posted By DualCore
synthesis

well you can port vhd files generated by ise into modelsim , creating new libraries i.e "simprim" , unisim . etc and then compile it .
Forum: VHDL 10-12-2006
Replies: 0
Views: 513
Posted By DualCore
Modelsim Post-synthesis

hi ,

i am trying to simulate a post-synthesis vhdl file generated by Xilinx Webpak , does anybody know how to include and use this file in modelsim independently ???:)
Forum: VHDL 09-27-2006
Replies: 3
Views: 4,669
Posted By DualCore
What about the Modelsim link that Matlab 2006B...

What about the Modelsim link that Matlab 2006B has , can you like just connect a 32bit bus into a VHDL module and see things working in realtime ?
has anyone tried that ?
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