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Search: Posts Made By: lucianofalbo
Forum: VHDL 11-11-2008
Replies: 7
Adc
Views: 709
Posted By lucianofalbo
Maybe I begin understanding something...then to...

Maybe I begin understanding something...then to make only a simple DAC I have to send the digital word that i want to convert to a PPM generator and send the PPM pulse to an analog low pass filter....
Forum: VHDL 11-10-2008
Replies: 7
Adc
Views: 709
Posted By lucianofalbo
I have read the block diagram for the PPM DAC in...

I have read the block diagram for the PPM DAC in your link but there is something basic I don't understand. What is the digital value to be converted?Is it PCM? How can I obtain an analogic value...
Forum: VHDL 11-09-2008
Replies: 7
Adc
Views: 709
Posted By lucianofalbo
last week i had not enough time to read...

last week i had not enough time to read accurately your documentation. I will do it in this week. Anyway please answer to this question:
Is it possible using only an FPGA (I have a spartan3) to...
Forum: VHDL 11-06-2008
Replies: 7
Adc
Views: 709
Posted By lucianofalbo
Thanks very much! I will look at the link and try...

Thanks very much! I will look at the link and try to understand what to do!
Bye
Luciano
Forum: VHDL 11-05-2008
Replies: 7
Adc
Views: 709
Posted By lucianofalbo
Adc

Can somebody help me with the code for an ADC? I just need an example...
Thanks.
Forum: VHDL 11-05-2008
Replies: 2
Views: 889
Posted By lucianofalbo
I have written a NCO code(hope it works well)....

I have written a NCO code(hope it works well). But now I ask your help for writing a vhdl code for an ADC(always in the project for my DDC).
Thanks
Forum: VHDL 11-03-2008
Replies: 2
Views: 889
Posted By lucianofalbo
Unhappy DDC and NCO

Dear all
I have to write a vhdl code of a DDC in Spartan3 FPGA. First of all I am trying to write the code for an NCO but, as I have understood reading from the web, I have to create and use a LUT...
Forum: VHDL 09-05-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Smile thanks jeppe

Dear Jeppe
I am happy to inform you that your last code with the FSM works properly!!!
I have discovered that I had a hardware problem in my B generator (the cable used for the data transmission...
Forum: VHDL 08-06-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Dear Jeppe I apologize for the delay but from...

Dear Jeppe I apologize for the delay but from yesterday I am on holiday and I can't work on my FPGA project up to 25 August. Anyway I say you that:
1) B can increase or decrease of one bit or zero...
Forum: VHDL 08-04-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Unhappy Not Work

Always the same problem
Forum: VHDL 08-04-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
No I have never used chipScope. I have seen the...

No I have never used chipScope. I have seen the different bits of B by a Scope
and B changes at the frequency of dataready that becomes high more or less 20-30 nsec after B has changed. So...
Forum: VHDL 08-04-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
??

Yes, I have used the code @#18(in the week end I can't use the FPGA). Dataready is the clock of the vector B. I have not understood your last suggestion. I can't take the B value at the falling edge...
Forum: VHDL 08-04-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Unhappy Not Work

Hi
Unfortunately also with your new changes the code has again the same problem
(for Bup and Benable).
Any other suggestions?
thanks
Forum: VHDL 08-01-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Unhappy tests not ok

Considering what happens I think you are really right! Howevere maybe I have not understood your suggestions. I have tried two ways without success.
I report here your FSM with the changes labelled...
Forum: VHDL 08-01-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Unhappy really the problem is again here

DEar Jeppe
I have written the FSM for the other process (Benable); unfortunately I have found a bug in the new process and thanks to this bug I have found a bug in the FSM codes you have sent me....
Forum: VHDL 07-31-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Red face thanks jeppe

Thank you very very much for your FSM. I have tried the first one and it seems it works! Wonderfull! You are great! And what about the process of my last post? Also in that case is it better to use...
Forum: VHDL 07-31-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Unhappy great problems

Thanks for your FSM code, I will try it. I have not tried it because I have found another problem in another process of the same entity. Maybe the problem source is the same. I am worried because the...
Forum: VHDL 07-29-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Unhappy why?

Dataready is 300 kHz signal that is high for about 1.6 microsecond. It becomes high about 10 nsec the new B is ready. clk50 is a 50 MHz signal. Why do you think this could be a problem?
Forum: VHDL 07-29-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Unhappy Not Work

I have used your new code(I have done copy and paste from your post)but it works worst than the others: I have only few pulses and not always in the same positions. :-(
Thanks for your past and...
Forum: VHDL 07-29-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Unhappy Not Work

Unfortunately your new code does not work. I am aware that the problem is mainly (only?) in this process (gatepr). The problem with your code and my code is that sometimes I have not the pulse....
Forum: VHDL 07-29-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Unhappy Not Work

DEar Jeppe thanks but your code does not work. I had already tried in that way.
thanks
Forum: VHDL 07-28-2008
Replies: 29
Views: 1,686
Posted By lucianofalbo
Unhappy two related process

Hi. I have not experience in vhdl but i need to make work this code! It is very important!
I explain the problem. I have a 24 bits vector as input (B). The input dataready is a signal that is high...
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