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Forum: VHDL 05-09-2011
Replies: 0
Views: 1,237
Posted By Tha
Having trouble on initialization of array signal

I am writing a register file..
and I want to assign some initial value to the array
my array have 128 entires and each entire is 128 bit long
however, no matter what format I tried to use..
it...
Forum: VHDL 04-10-2011
Replies: 4
Views: 3,946
Posted By Tha
Okay, just after I post this thread , I found out...

Okay, just after I post this thread , I found out why my code doesn't work.

"Note that this library doesn't allow you to do comparisons on std_logic_vector values. That's because it's impossible...
Forum: VHDL 04-10-2011
Replies: 4
Views: 3,946
Posted By Tha
Question on Comparing two std logic vecter

Hi, I am new on VHDL, and I am writing a code that comparing two 32 bits std_logic_vector. If they are equal, a result of all one bits is produce, otherwise, a result of all zero bits is produce....
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