Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Search Forums > Search Results

Showing results 1 to 19 of 19
Search took 0 seconds.
Search: Posts Made By: picnanard
Forum: VHDL 11-22-2010
Replies: 0
Views: 696
Posted By picnanard
fpga board with parallel dac?

Hello,

Sorry for this small off board query, but I search a fpga(xilinx,Altera…) board with a parallel dac (not spi,i2c)? Someone can advise to me.

Thank you.
Forum: VHDL 01-19-2010
Replies: 0
Views: 797
Posted By picnanard
reset on cosimulation box (simulink-modelsim)

When can I set an asynchronous reset for simulink co simulation box (attach file)
I can launch modelsim with simulink but all signals are not define, because reset signal is not set.

Someone can...
Forum: VHDL 03-14-2009
Replies: 1
Views: 612
Posted By picnanard
my sample mixed vhdl&verilog

I try this mixed project in modelsim
result
# vsim work.bench
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.std_logic_textio(body)
#...
Forum: VHDL 03-14-2009
Replies: 1
Views: 612
Posted By picnanard
Thumbs up (refine question) vhdl and verilog simualtion

Hi,

Sorry for second thread, but i must be find solution for my job.

I want launch simulation with architecture see attach file.
I'm two component one in vhdl and other in verilog model inside...
Forum: VHDL 03-12-2009
Replies: 0
Views: 489
Posted By picnanard
Use verilog component in vhdl bench

How can i use in same test bench.vhd two IP ::captain:
One IP in vhdl and other IP in verilog,
Perhaps i must be use netlist of verilog IP?
On modelsim and ghdl can I instantiate these IP on vhdl...
Forum: VHDL 09-01-2008
Replies: 0
Views: 550
Posted By picnanard
when sampled signal falling or rising edge

I have a very simple question? With a simple example:
Inside same fpga. Inside one process I generate a signal wide one period on rising edge.
If I want test this signal inside another process on...
Forum: VHDL 03-18-2008
Replies: 0
Views: 540
Posted By picnanard
to view vhdl variable with gtkwave

Hello,

When can i see vhdl variable with gtkwave.

Currently i use three command inside cygwin:
ghdl -a --ieee=synopsys -fexplicit --std=93 bench.vhd
ghdl -c --ieee=synopsys -fexplicit...
Forum: VHDL 07-24-2007
Replies: 0
Views: 423
Posted By picnanard
General question on access SRAM

I want control the read and write (SRAM single data port) with FPGA I want stick a read cycle after write cycle. See below
CS ----\_________________/------
RD ----\_______/-----------------
WR...
Forum: VHDL 07-11-2007
Replies: 0
Views: 300
Posted By picnanard
write in same file with several procedure

hello,

I want inside several procedure write in same file
but i don't know when i pass the message (TEXT) procedure to process.
Process where i write the line.
...
Forum: VHDL 03-20-2007
Replies: 1
Views: 359
Posted By picnanard
Simulation IPprocessor and FPGA

Hello?

I purchase a software where i could compile and simulate
a core processor in fpga with an architecture vhdl in same FPGA.
:captain:

Thank you for you idea.
Forum: VHDL 03-20-2007
Replies: 6
Views: 3,307
Posted By picnanard
answer

Excuse me for this delay.
You use std_logic_textio in vhdl bench file
and this file bench must no appear in project file.
You must be place this file bench in assignement setting simualtion in...
Forum: VHDL 03-16-2007
Replies: 6
Views: 3,307
Posted By picnanard
answer

Yes if your file appear in project-settings-file, this file belong project.
Forum: VHDL 03-15-2007
Replies: 6
Views: 3,307
Posted By picnanard
answer

I have the same problem the last week
This file is a bench file for read or write simulate file.
You must be to aime this file in tools-simulate-testbench
This bench file must not appear in...
Forum: VHDL 03-15-2007
Replies: 0
Views: 526
Posted By picnanard
std_logic_vector 64bits with data 8 bits

:oops: Hello,

excuse me for the last message this forum is in english
Ok i want build an std_logic_vector 64bits with eight std_logic_vector 8bits

Thank for your idea.
Forum: VHDL 03-15-2007
Replies: 0
Views: 395
Posted By picnanard
constuire un bus 64bits avec des data 8bits

salut a tous,

Comment peut on construire un std_logic_vector(63 downto 0)
a partir de 8 std_logic_vector(7downto 0)
donc comment constuire une data 64bits avec 8 data de 8bits
en vhdl.:flute: ...
Forum: VHDL 03-12-2007
Replies: 0
Views: 972
Posted By picnanard
message no data on modelsim

Hello,

I have design with several layer.
(component consist of components)
I use a vhdl file bench for test my design with modelsim
No problem when i see the signal declared on the bench
i can...
Forum: VHDL 03-07-2007
Replies: 0
Views: 545
Posted By picnanard
Question link betwen signal vhdl bench and entity (quartus2&modelsim)

Hello,

i have two vhdl prog
FIFO(RTL)
entity2(arch2)

I see these programs in project windows of quartus 2.

i have another prog bench in vhdl
this vhdl bench is aimed by quartus in...
Forum: VHDL 03-07-2007
Replies: 1
Views: 3,588
Posted By picnanard
i find answer

ok i have found a answer if someone is interresting
we must be use modelsim altera for use test bench.vhdl
it is EDA sotfware.
:beer:
Forum: VHDL 03-06-2007
Replies: 1
Views: 3,588
Posted By picnanard
VHDL test bench with quartus 2? How ?

Hello,

I want use test bench in vhdl.
I use whdl code for simulate input signal of my design.
This bench also writes in text file output signal.
Which EDA simulator i need, if I want to do...
Showing results 1 to 19 of 19

 
Forum Jump


Advertisments