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Forum: Hardware 10-27-2009
Replies: 0
Views: 2,368
Posted By allsey_1987
Question VHDL and EDK: Custom IP core containing an array as a port using EDK

I have my doubts that anyone will be able to help me on this one, but i give it a try anyway:

I'm integrating a soft-core microblaze cpu into a design for a control system. I have created a custom...
Forum: VHDL 07-27-2009
Replies: 2
Views: 494
Posted By allsey_1987
Arrow a single std_logic can only take values real...

a single std_logic can only take values real values i.e. '1' or '0'...

maybe a simple if statement will solve your problem

signal theBit : std_logic;
signal theVector, ans :...
Forum: VHDL 07-27-2009
Replies: 4
Views: 1,436
Posted By allsey_1987
Question i think what you want to do is this: signal...

i think what you want to do is this:

signal RED : std_logic_vector(7 downto 0);
signal GREEN : std_logic_vector(7 downto 0);
signal BLUE : std_logic_vector(7 downto 0);

signal Counter:...
Forum: VHDL 07-27-2009
Replies: 4
Views: 1,436
Posted By allsey_1987
mmm... i think you might need to do some reading...

mmm... i think you might need to do some reading on VHDL...

You do realise for every iteration of a process a signal can only be assigned to once. and this assignment doesn't take effect until the...
Forum: VHDL 07-27-2009
Replies: 1
Views: 910
Posted By allsey_1987
very very unlikely ;-) the process of...

very very unlikely ;-)

the process of extracting code from an FPGA would be a unsupported feature... furthermore FPGA's contain volatile configurations, meaning that your configuration is probably...
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