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Search: Posts Made By: veenamgp
Forum: VHDL 09-20-2006
Replies: 0
Views: 482
Posted By veenamgp
Error in variable assignment

Hi,

I want to assign a value to variable and then use this value for assigning for a signal. Such as

c<= (a and b) or (d:= a and b);

but its giving me an error

near ":=": expecting: ')' ...
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