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Forum: VHDL 01-10-2009
Replies: 2
Views: 493
Posted By uhu01
Hi, I'm not a VHDL Pro, but the first thing...

Hi,

I'm not a VHDL Pro, but the first thing that comes to my mind is something like:

constant zeroes : std_logic_vector(11 downto 0) := "00000000000";
some_signal <= "1010" & zeroes;
...
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