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Forum: VHDL 05-28-2010
Replies: 0
Views: 465
Posted By mreister
VHDL test benchs? How the big boys do it

I would like to know what is the most common ways test benches are written in when verifying a VHDL design? I have used modelsim in the past with do files with some logic mixed in with tcl scripts....
Forum: VHDL 05-25-2010
Replies: 1
Views: 2,952
Posted By mreister
Nevermind solved

I forgot the include a '>' in one of the portmap declaration..... didn't seem to be a very accurate error message
Forum: VHDL 05-25-2010
Replies: 1
Views: 2,952
Posted By mreister
Type of actual ports is not compatible with type of ports of entity.

I have a realy anoying error on my hands. I think I understand what its trying to tell me but, I cant seem to find the mismatch. As I understand it the error, which apears in the title of this post,...
Forum: VHDL 05-16-2010
Replies: 1
Views: 1,208
Posted By mreister
VHDL statement execution order

Ok, I am still learning VHDL and I am having some problems with execution order of statements. Take for example the following code:

entity add_w_carry is
port(
a,b: in std_logic_vector(3...
Forum: VHDL 09-16-2008
Replies: 5
Views: 789
Posted By mreister
Thanks that worked great.

Thanks that worked great.
Forum: VHDL 09-12-2008
Replies: 5
Views: 789
Posted By mreister
type channel_output_array is array (0 to...

type channel_output_array is array (0 to 3,integer range 0 to 6) of std_logic_vector ( 31 downto 0);
type channel_selection_array is array ( 0 to 3,integer range 0 to 6) of bit;

Here they are.
Forum: VHDL 09-11-2008
Replies: 5
Views: 789
Posted By mreister
Fatal Error Modelsim Ok Xilinx

I am running into a frustrating problem. I have a function that returns x"0000" as the default value and assigns its value to a signal. The files syntax is correct accourding to xilinx, but when i...
Forum: VHDL 09-11-2008
Replies: 1
Views: 653
Posted By mreister
Procedures-functions Vs Processes?

I am still having difficulty understanding how functions-procedures are executed in VHDL. What I donít understand is how long it takes them to execute. Do they execute almost instantly? Meaning will...
Forum: VHDL 09-03-2008
Replies: 6
Views: 1,321
Posted By mreister
Thank you all very much for your replies. Yes, i...

Thank you all very much for your replies. Yes, i was intending the statement to run sequentially just like in C. However, what i dont get is how is it physically implemented on the FPGA? If it is not...
Forum: VHDL 08-19-2008
Replies: 0
Views: 510
Posted By mreister
File I/O problem. VHDL

I am trying to write information to a text file in VHDL. Here is my code



type frame_data is array (31 downto 0) of std_logic_vector(31 downto 0);



type my_file is file of...
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