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Search: Posts Made By: aloque
Forum: VHDL 05-01-2009
Replies: 2
Views: 706
Posted By aloque
try pipelined CORDIC on Vector mode or search for...

try pipelined CORDIC on Vector mode or search for another type of decision strategy.
Forum: VHDL 03-13-2009
Replies: 7
Views: 991
Posted By aloque
The way I do to use unisims with ghdl: Library...

The way I do to use unisims with ghdl:
Library UNISIM;
use UNISIM.vcomponents.all;

In project path I make a dir called unisim and then copy all files of vhdl/src/unisims in ISE install path in...
Forum: VHDL 01-22-2009
Replies: 4
Views: 4,248
Posted By aloque
To infer a ram lut based: Each Slice have two...

To infer a ram lut based:
Each Slice have two Logic Cell and each logic cell have a LUT (SRAM 16 word x 1 bit)


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use...
Forum: VHDL 01-15-2009
Replies: 1
Views: 903
Posted By aloque
Solved

Sorry. I made a big mistake in test bench file :lol: ,

I had connected doB to PortB and PortD, oops, many days checking why didn't working but was a simple finger error.

Now is working
:lol:...
Forum: VHDL 01-14-2009
Replies: 1
Views: 903
Posted By aloque
Quad Port RAM

I'm using the Spartan 3E starter kit and I just trying to make a Quad Port RAM with the reading and writing ports independent. The code is the next:
First infer a Dual Port RAM with the reading and...
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