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Search: Posts Made By: karlwijk
Forum: VHDL 04-17-2007
Replies: 3
Views: 620
Posted By karlwijk
Hi, thanks. Can you explain why my solution...

Hi, thanks. Can you explain why my solution creates a problem? Under what signal conditions? Is it, for instance, if you get clear='1' and set='1' at the same time?

Kind regards,
Karl
Forum: VHDL 04-16-2007
Replies: 3
Views: 620
Posted By karlwijk
if/elsif problem

Hello, I have a problem with the following construct:

process(clk, reset_n)
begin
if (reset_n = '0') then
out <= '0';
elsif (clk'event and clk = '1') then
if (clear = '1') then
...
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