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Search: Posts Made By: kpram
Forum: VHDL 11-15-2007
Replies: 0
Views: 941
Posted By kpram
clock-domain-crossing simulation in Altera

Hi all

Does anyone knows of a way to tell Quartus that a particular FF is a clock-domain-crossing FF so that post-route netlist instantiates a FF for that, which does not propagate "X".

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