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Forum: VHDL 03-15-2011
Replies: 4
Views: 1,900
Posted By westocl
VHDL Sensitivity (Clock Delay Question)

Thanks jeppe for your reply and the link.

I have one last question having read the link. What about the situation where one assigns a variable to a signal or a signal to a variable??

Being...
Forum: VHDL 03-11-2011
Replies: 4
Views: 1,364
Posted By westocl
Weird XST error initializing record type on reset

I don't use record types much because I havent seen much benefit to them except for maybe code clarity, so i am not positive about the syntax, but it looks like

six_vect_inst <= (others =>...
Forum: VHDL 03-08-2011
Replies: 2
Views: 2,587
Posted By westocl
DIfference between function and procedure

Hello,

I've never really understood the difference between a function and a
procedure in VHDL. I've read that a function returns 1 value whereas a
procedure can return multiple values? Could...
Forum: VHDL 03-07-2011
Replies: 4
Views: 1,900
Posted By westocl
VHDL Sensitivity (Clock Delay Question)

I have a question about whether two processes syncronized by the same clock will alway create a clock delay or can you remove the clock delay by changing the sensitivty list.

here is an example.
...
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