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Search: Posts Made By: dziadek
Forum: VHDL 01-27-2007
Replies: 0
Views: 451
Posted By dziadek
Problem with I/O files.

Hi.
I've got problem with writing signal values to file. I just can't write any data to text file. For example I wrote this code:

USE STD.TEXTIO.all;

architecture beh of io is
signal...
Forum: VHDL 12-17-2006
Replies: 0
Views: 530
Posted By dziadek
connection

Hi.

I've got 2 blocks
first block has output:

out : std_logic_vector[7 downto 0]

and input of the second block:

in: std_logic_vector[15 downto 0]
Forum: VHDL 12-04-2006
Replies: 0
Views: 645
Posted By dziadek
multiplier

Hi.

I'm beginner in vhdl and I have simple question: How to implement multiplier.

a*b=c; where a is fractional for example 0.123456, b is signed integer and c is a result in desired resolution,...
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