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Search: Posts Made By: joris
Forum: VHDL 06-19-2012
Replies: 9
Views: 1,043
Posted By joris
But in this case you'd want counter <= (counter +...

But in this case you'd want counter <= (counter + 1) mod 7;
Forum: VHDL 05-07-2012
Replies: 1
Views: 676
Posted By joris
Intermediate variables don't imply registers, so...

Intermediate variables don't imply registers, so both codes should be exactly equivalent.

Variables only imply registers when their values are being read while they haven't previously been set in...
Forum: VHDL 03-22-2012
Replies: 6
Views: 878
Posted By joris
This compiles (untested though) :library ieee; ...

This compiles (untested though) :library ieee;
use ieee.std_logic_1164.all;

entity delay_gate is

generic (
ACTIVE_EDGE : std_logic := '1';
MAX_DELAY_GATE_CYCLES : integer := 7
);
Forum: VHDL 03-02-2012
Replies: 1
Views: 691
Posted By joris
Might try something like, request <= (size -...

Might try something like,

request <= (size - 1 downto 10 => '0') & datain;
Forum: VHDL 02-25-2012
Replies: 1
Views: 972
Posted By joris
I think you can simply have,variable x, y :...

I think you can simply have,variable x, y : unsigned(7 downto 0);
variable z : unsigned(7 downto 0);

z := x * y; -- drops 8 most significant bits
Forum: VHDL 12-05-2011
Replies: 3
Views: 1,612
Posted By joris
you'll have to post the relevant code for anyone...

you'll have to post the relevant code for anyone to be able to help.
Double check inputs and outputs, as well as setting correct 'generic' values
Forum: VHDL 11-24-2011
Replies: 1
Views: 1,126
Posted By joris
Are you sure the entity is called 'subtractor_n'...

Are you sure the entity is called 'subtractor_n' instead of 'substractor_n' ?
Forum: VHDL 11-24-2011
Replies: 3
Views: 965
Posted By joris
I think the second option would look similar to...

I think the second option would look similar to this:Library IEEE;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;

Entity counter is
port
(
clk : in std_logic;...
Forum: VHDL 11-12-2011
Replies: 10
Views: 37,012
Posted By joris
Given that you are talking about generics, you...

Given that you are talking about generics, you could just calculate the length 'compile-time' using a log2() function (I think you'll have to write the function yourself, but that is trivial)
Forum: VHDL 11-12-2011
Replies: 4
Views: 1,620
Posted By joris
I think the easiest design is using one process...

I think the easiest design is using one process which is driven by a clock (and perhaps an asynchronous reset signal).
Forum: VHDL 10-29-2011
Replies: 1
Views: 907
Posted By joris
1 is 0001 5 is 0101 9 is 1001 13 is...

1 is 0001
5 is 0101
9 is 1001
13 is 1101
noticing a pattern?

15 is 1111
that's an odd one, will need a bit of extra logic
Forum: VHDL 10-29-2011
Replies: 4
Views: 1,620
Posted By joris
You can avoid a lot of difficulties by...

You can avoid a lot of difficulties by redesigning the code,
when you have only one clock'ed process, you won't have latches inferred.
That way you also get rid of the state/nextstate juggling.
Forum: VHDL 10-29-2011
Replies: 4
Views: 1,620
Posted By joris
You are assigning to State in the second process...

You are assigning to State in the second process a few times, surely that's wrong (they should be replaced with assignments to NextState)

I think you should only list 'state' in the sensitivity...
Forum: VHDL 10-07-2011
Replies: 4
Views: 2,261
Posted By joris
The only thing I can think of is that I don't see...

The only thing I can think of is that I don't see this:use work.my_data_types.all;in the code you just posted.
However if that's the cause, it would seem Modelsim should complain about not finding...
Forum: VHDL 10-06-2011
Replies: 4
Views: 2,261
Posted By joris
You should use exactly the same types in the...

You should use exactly the same types in the component declaration as in the entity declaration:

library work;
use work.my_data_types.all;

ENTITY gen_mux_vhd_tst IS
END gen_mux_vhd_tst;...
Forum: VHDL 09-24-2011
Replies: 3
Views: 1,920
Posted By joris
I think you can do this by having the recursion...

I think you can do this by having the recursion on entity level instead of function level.
In order to do this,

Move the code outside the function, into the architecture body
Replace variables...
Forum: VHDL 07-28-2011
Replies: 3
Views: 1,093
Posted By joris
if you put code between -- code ...

if you put code between

-- code

then the formatting will remain
Forum: VHDL 07-27-2011
Replies: 3
Views: 1,577
Posted By joris
my guess would be that some files were not...

my guess would be that some files were not installed correctly
Forum: VHDL 07-04-2011
Replies: 6
Views: 2,046
Posted By joris
hmm I guess it should've been unsigned'('0'...

hmm I guess it should've been

unsigned'('0' & a)

"casting" the implicit vector to the unsigned type.
Guess that's the case I always get wrong
Forum: VHDL 07-01-2011
Replies: 6
Views: 2,046
Posted By joris
I don't know, it may be the Xilinx tool...

I don't know, it may be the Xilinx tool recommends it.
The reason to avoid that one, is that it isn't truly standardized -- different tools may have incompatibilities.

BTW, just to state the...
Forum: VHDL 07-01-2011
Replies: 6
Views: 2,046
Posted By joris
You can sum variables declared as unsigned (or...

You can sum variables declared as unsigned (or integer), but not std_logic;

You are trying to add two one-bit values and store the result in a one bit, that can't work since 1+1 = 2 = (10)binary,...
Forum: VHDL 06-08-2011
Replies: 1
Views: 1,769
Posted By joris
A space is required between 'port' and 'map'

A space is required between 'port' and 'map'
Forum: VHDL 05-24-2011
Replies: 1
Views: 839
Posted By joris
I think it's simply saying that the synthesizer...

I think it's simply saying that the synthesizer found out that, that particular variable/signal idex_signimm, the mentioned bits (8-0) can only have a value of 0 because of the code.
If this is...
Forum: VHDL 05-14-2011
Replies: 1
Views: 1,764
Posted By joris
I think this is what you meant, library...

I think this is what you meant,


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Alu_Control is
Port ( AluOp : in...
Forum: VHDL 05-12-2011
Replies: 1
Views: 923
Posted By joris
I think it's fine (though one might say it may be...

I think it's fine (though one might say it may be "nicer" to use a variable to make it more explicit the old value is copied rather than the new one)

BTW it is unnecessary FRAME is listed in the...
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