Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Search Forums > Search Results

Showing results 1 to 1 of 1
Search took 0 seconds.
Search: Posts Made By: Luca D.
Forum: VHDL 03-05-2010
Replies: 0
Views: 499
Posted By Luca D.
When others case and Synthesis

Hi all!
I've just started to study how the synthesis process works and can't find any information about what happens when values different from '1' and '0' are used for a std_logic signal.
Showing results 1 to 1 of 1

Forum Jump