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Search: Posts Made By: kunal.bandekar
Forum: VHDL 05-24-2011
Replies: 4
Views: 8,753
Posted By kunal.bandekar
Lightbulb Logic_vector to Natural

--CONSTANT declaration
constant COUNTER_LOGIC : integer := 8;

signal count : std_logic_vector (COUNTER_LOGIC-1 downto 0);


-- Felt it very useful if you want to avoid writing...
Forum: VHDL 05-23-2011
Replies: 7
Views: 3,627
Posted By kunal.bandekar
Bit wise oring

--Bit wise or generator
process (busy_gen_temp)
variable b_var : std_logic;
begin

b_var := '0';
for i in 0 to (CHANNEL_LENGTH_TOP-1) loop
b_var := b_var or busy_gen_temp(i);
-- This...
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