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Search: Posts Made By: Mister_J
Forum: VHDL 08-30-2013
Replies: 1
Views: 315
Posted By Mister_J
Reflexions about a new HDL language

Hello,

I am thinking about defining a new HDL language, that will be more modern than VHDL (and Verilog) and allow a little higher level behavioral description than VHDL. For this language, I am...
Forum: VHDL 07-02-2012
Replies: 2
Views: 950
Posted By Mister_J
Did you try to make a GHDL waveform file instead...

Did you try to make a GHDL waveform file instead of a vcd file (see http://ghdl.free.fr/ghdl/Simulation-options.html) ?

Jonas
Forum: VHDL 07-02-2012
Replies: 1
Views: 662
Posted By Mister_J
Hi, The problem is at line 183 : carry...

Hi,

The problem is at line 183 :

carry : entity work.or_xnor_ncl

because carry is already the name of one of your signals, then you have to rename it.

Jonas
Forum: VHDL 06-29-2012
Replies: 7
Views: 683
Posted By Mister_J
I think that the solution from Rob Gaddi is the...

I think that the solution from Rob Gaddi is the best one, but if you want to do a division, here is
how you can do :

You could use the new fixed point type from fixed_pkg and use the function...
Forum: VHDL 06-29-2012
Replies: 2
Views: 688
Posted By Mister_J
It seems that MXE is no longer available...

It seems that MXE is no longer available (http://www.xilinx.com/tools/mxe.htm). You could download the regular Modelsim with native linux support from here :...
Forum: VHDL 06-29-2012
Replies: 2
Views: 617
Posted By Mister_J
I forgot one thing : how the resizing should work...

I forgot one thing : how the resizing should work when doing arithmetics on integers with representation clause :

Here is an example :
subtype My_Natural is Base_Natural;
signal A_s, B_s :...
Forum: VHDL 06-29-2012
Replies: 2
Views: 617
Posted By Mister_J
Actually, declaring a integer with a...

Actually, declaring a integer with a representation clause would be 3 times longer as declaring (un)signed signals :

subtype My_Integer_8 is Base_Integer;
for My_Integer_8 use Std_uLogic_Vector...
Forum: VHDL 06-28-2012
Replies: 2
Views: 617
Posted By Mister_J
What about a new attribute to access the physical representation of a signal ?

Hello,

It seems to me it can be a good idea to add to VHDL a new attribute 'repr in order to be able to access the representation of a signal (bits) that is normally not accessible on most types...
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