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Search: Posts Made By: gzidude
Forum: VHDL 06-02-2008
Replies: 5
Views: 442
Posted By gzidude
Which spartan3 board do you have? It would help...

Which spartan3 board do you have? It would help if we knew what goodies are already connected to your board so your project won't have to cost you anything extra.
Forum: VHDL 05-22-2008
Replies: 0
Views: 453
Posted By gzidude
Xistinks

Is there some some ridiculously small project size limit or some other limiting factor that will cause Xilinx ISE (both v6 and v10) to tell me that everything is perfectly fine, when it, according to...
Forum: VHDL 04-29-2008
Replies: 7
Views: 869
Posted By gzidude
Speed is most important in this design. I'm...

Speed is most important in this design. I'm probably off my rocker thinking this can be done in few clocks.
Forum: VHDL 04-29-2008
Replies: 7
Views: 869
Posted By gzidude
fifty-five

fifty-five
Forum: VHDL 04-29-2008
Replies: 7
Views: 869
Posted By gzidude
I know all the ways to build standard...

I know all the ways to build standard multipliers. I was asking if there were any tricks to square numbers to reduce hardware at synthesis.
Forum: VHDL 04-28-2008
Replies: 7
Views: 869
Posted By gzidude
squaring numbers

Does anybody know if there are any tricks to simply the process of multiplication if all I'm doing is squaring numbers (multiplying them by themselves)?
Forum: VHDL 04-21-2008
Replies: 7
Views: 3,874
Posted By gzidude
Talking sweet!

You guys are my HEROS!!!!!
Forum: VHDL 04-02-2008
Replies: 6
Views: 2,344
Posted By gzidude
Dang! I really have been away.

Dang! I really have been away.
Forum: VHDL 04-02-2008
Replies: 5
Views: 4,654
Posted By gzidude
Are you saying you want to code up an ADC in...

Are you saying you want to code up an ADC in VHDL? or are you saying you have an ADC that you'd like to interface and would like to know VHDL so you can do it?

You can not code up an ADC in VHDL. ...
Forum: VHDL 04-02-2008
Replies: 6
Views: 2,344
Posted By gzidude
Sorry about that. I just modified my previous...

Sorry about that. I just modified my previous post. Perhaps that'll help. I've been away from VHDL for a while and have gotten pretty rusty.
Forum: VHDL 04-02-2008
Replies: 6
Views: 2,344
Posted By gzidude
Post this might work

Since you need to check 64 bits for events which can occur at any time, you need to generate concurrent hardware to check each one. This code might work:

for i in vec'range generate
if...
Forum: VHDL 02-29-2008
Replies: 1
Views: 594
Posted By gzidude
Thumbs down lame

if you want me to do your homework for you, I take cash, money order, or bank certified check

now go away
Forum: VHDL 02-25-2008
Replies: 5
Views: 618
Posted By gzidude
Mark, I know what you mean. However, I have...

Mark,
I know what you mean. However, I have seen that a lower level description looks fine on an RTL viewer. High level code looks pretty bad though. The code given above shouldn't look too bad.
Forum: VHDL 02-25-2008
Replies: 3
Views: 620
Posted By gzidude
off topic for a minute

Off topic for a minute.

I have never seen the kind of 'dot-notation' used in that code:



I'm specifically talking about the V.R and V.I. This particular syntax is new to me. I'd like to...
Forum: VHDL 02-19-2008
Replies: 2
Views: 571
Posted By gzidude
yup

isn't dumpvars a verilog thing? I'll look it up eventually.
Forum: VHDL 02-19-2008
Replies: 9
Views: 492
Posted By gzidude
why?

You guys both wrote the same code except John used <= and Mike used :=
Forum: VHDL 02-17-2008
Replies: 1
Views: 625
Posted By gzidude
jim

Your code is making two assignments to jim at the same time. Your compiler should puke all over you. It assigns jim(4) to '0' and jim(4) to '1' concurrently since they're being clocked together.
...
Forum: VHDL 02-17-2008
Replies: 2
Views: 433
Posted By gzidude
Question ????

Is that sort of thing the kind of spam you get around here, or did anyone enjoy reading it?
Forum: VHDL 02-17-2008
Replies: 0
Views: 441
Posted By gzidude
Question partioning made easy?

Is it possible to partition a section of hardware within VHDL, at the code level? Not necessarily as part of the VHDL standard, but maybe as a vendor specific addition. That way the logic...
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